SPI_HOST Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.000s	191.291us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	63.395us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	21.639us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	110.860us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	155.308us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	79.572us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	21.639us	1	1	100.00
		spi_host_csr_aliasing	3.000s	155.308us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	18.548us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	22.083us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	60.906us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	69.002us	1	1	100.00
		spi_host_error_cmd	2.000s	16.798us	1	1	100.00
		spi_host_event	7.000s	824.158us	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	62.776us	1	1	100.00
V2	speed	spi_host_speed	4.000s	62.776us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	62.776us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	78.355us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	41.717us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	62.776us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	62.776us	1	1	100.00
V2	duplex	spi_host_smoke	9.000s	191.291us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	9.000s	191.291us	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	377.399us	1	1	100.00
V2	spien	spi_host_spien	4.000s	245.044us	1	1	100.00
V2	stall	spi_host_status_stall	41.000s	3.044ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	32.442us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	69.002us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	21.282us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	25.111us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	52.644us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	52.644us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	63.395us	1	1	100.00
		spi_host_csr_rw	3.000s	21.639us	1	1	100.00
		spi_host_csr_aliasing	3.000s	155.308us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	15.878us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	63.395us	1	1	100.00
		spi_host_csr_rw	3.000s	21.639us	1	1	100.00
		spi_host_csr_aliasing	3.000s	155.308us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	15.878us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	60.223us	1	1	100.00
		spi_host_sec_cm	3.000s	135.709us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	60.223us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.667m	15.012ms	1	1	100.00
		TOTAL			26	26	100.00