SRAM_CTRL/MAIN Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.080s	1.051ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.970s	29.496us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.980s	12.835us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	151.492us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.900s	157.952us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.960s	369.886us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.980s	12.835us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	157.952us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.434m	159.166ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.046m	5.281ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.456m	57.560ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.300m	3.305ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.687m	22.212ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.260m	32.807ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	51.440s	26.695ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.652m	27.145ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	21.830s	3.281ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.050m	15.947ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	13.130s	1.487ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.120s	746.302us	1	1	100.00
		sram_ctrl_throughput_w_readback	18.020s	3.327ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	19.830s	548.143us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.150s	362.833us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	32.804m	77.822ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.930s	39.932us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.860s	66.477us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.860s	66.477us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.970s	29.496us	1	1	100.00
		sram_ctrl_csr_rw	0.980s	12.835us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	157.952us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	45.028us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.970s	29.496us	1	1	100.00
		sram_ctrl_csr_rw	0.980s	12.835us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	157.952us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	45.028us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	22.550s	14.770ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
		sram_ctrl_tl_intg_err	2.380s	1.264ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.380s	1.264ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.830s	548.143us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.830s	548.143us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.980s	12.835us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.652m	27.145ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.652m	27.145ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.652m	27.145ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	51.440s	26.695ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.980s	674.929us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	22.550s	14.770ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.340s	2.793ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.080s	1.051ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.080s	1.051ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.652m	27.145ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	51.440s	26.695ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.080s	1.051ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.030s	9.122us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	29.720s	4.273ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.82009555761402837714867095907926555321137659018469625607083123470525295709060
      Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9122127 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9122127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---