SYSRST_CTRL Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: `ba7ffa6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.240s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	5.270s	2.477ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.130s	2.148ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.950s	2.513ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	10.710s	6.056ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.720s	2.056ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	51.690s	76.220ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.500s	2.207ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.750s	2.072ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.720s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.500s	2.207ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	4.391m	132.264ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.442m	45.211ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	10.287m	316.875ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	1.850s	3.665ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	5.620s	2.510ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.500s	2.257ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	1.700s	4.635ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.530s	2.628ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	6.240s	9.749ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.226m	37.829ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	3.770s	7.180ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.300s	2.024ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.520s	2.033ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.690s	2.217ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.690s	2.217ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	10.710s	6.056ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.720s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.500s	2.207ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	25.490s	9.552ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	10.710s	6.056ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.720s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.500s	2.207ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	25.490s	9.552ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	44.480s	22.008ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	22.950s	22.310ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	22.950s	22.310ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.220s	18.629ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:121) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (* [*] vs * [*])

has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.5369860708519935555890587648290510760450510105957847596934602039710878776477
Line 458, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18589322716 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 18592945136 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 10/10
  UVM_INFO @ 18629275656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---