UART Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.980s	313.549us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.550s	12.462us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.570s	14.763us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.160s	683.535us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	48.541us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.040s	94.709us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.570s	14.763us	1	1	100.00
		uart_csr_aliasing	0.750s	48.541us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	36.450s	98.231ms	1	1	100.00
V2	parity	uart_smoke	1.980s	313.549us	1	1	100.00
		uart_tx_rx	36.450s	98.231ms	1	1	100.00
V2	parity_error	uart_intr	19.810s	27.446ms	1	1	100.00
		uart_rx_parity_err	23.580s	75.938ms	1	1	100.00
V2	watermark	uart_tx_rx	36.450s	98.231ms	1	1	100.00
		uart_intr	19.810s	27.446ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.560m	154.608ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	39.570s	30.238ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	4.250s	16.441ms	1	1	100.00
V2	rx_frame_err	uart_intr	19.810s	27.446ms	1	1	100.00
V2	rx_break_err	uart_intr	19.810s	27.446ms	1	1	100.00
V2	rx_timeout	uart_intr	19.810s	27.446ms	1	1	100.00
V2	perf	uart_perf	7.668m	15.286ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.340s	9.909ms	1	1	100.00
V2	line_loopback	uart_loopback	5.340s	9.909ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	20.690s	18.345ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	10.710s	5.092ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.620s	1.401ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.250s	4.860ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.659m	300.556ms	1	1	100.00
V2	stress_all	uart_stress_all	23.465m	138.198ms	1	1	100.00
V2	alert_test	uart_alert_test	0.590s	60.962us	1	1	100.00
V2	intr_test	uart_intr_test	0.680s	12.564us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.780s	79.700us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.780s	79.700us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.550s	12.462us	1	1	100.00
		uart_csr_rw	0.570s	14.763us	1	1	100.00
		uart_csr_aliasing	0.750s	48.541us	1	1	100.00
		uart_same_csr_outstanding	0.870s	29.672us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.550s	12.462us	1	1	100.00
		uart_csr_rw	0.570s	14.763us	1	1	100.00
		uart_csr_aliasing	0.750s	48.541us	1	1	100.00
		uart_same_csr_outstanding	0.870s	29.672us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.030s	223.916us	1	1	100.00
		uart_tl_intg_err	1.080s	1.661ms	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.080s	1.661ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.200s	6.674ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.11327355821187838026275966228248991136565909000251745277508254499279387345907
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 17838782014 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 17838782014 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 17875952014 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 17875962014 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 17875972014 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 93 [0x5d]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.17904356669542713598416785520108985480873128479107435266637342150707381458996
      Line 147, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5275328832 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 5287024414 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 5288502666 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 5639413604 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/928
        UVM_ERROR @ 5812716912 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0