CHIP Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: `ba7ffa6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.562m	2.771ms	1	1	100.00
		chip_sw_example_rom	1.145m	2.961ms	1	1	100.00
		chip_sw_example_manufacturer	2.038m	2.912ms	1	1	100.00
		chip_sw_example_concurrency	2.615m	3.194ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.496m	4.679ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.069m	3.963ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.954m	6.125ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.348h	33.446ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	47.280s	2.812ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.348h	33.446ms	1	1	100.00
		chip_csr_rw	3.069m	3.963ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	10.000s	212.998us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.883m	4.183ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.883m	4.183ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.883m	4.183ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.525m	3.998ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.525m	3.998ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.103m	3.848ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.771m	4.775ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.695m	3.767ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	26.572m	12.315ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.478m	7.810ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.684m	8.950ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.479m	5.319ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.479m	5.319ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.709m	3.206ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.887m	4.993ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.641m	4.441ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.193m	4.591ms	1	1	100.00
		chip_tap_straps_testunlock0	3.129m	3.855ms	1	1	100.00
		chip_tap_straps_rma	6.614m	6.517ms	1	1	100.00
		chip_tap_straps_prod	17.330m	15.547ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.491m	2.451ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.707m	9.134ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.591m	5.841ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.591m	5.841ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.923m	7.948ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	33.437m	20.575ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.175m	4.718ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.313m	5.067ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.722m	18.590ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.965m	2.783ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.111m	6.516ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.726m	3.226ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.114m	11.886ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.784m	3.361ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.423m	5.346ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.162m	2.754ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.733m	3.211ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.577m	5.346ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.569m	5.148ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.913m	2.720ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.569m	5.148ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.887m	2.825ms	1	1	100.00
		chip_sw_aes_smoketest	2.642m	2.929ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.879m	3.558ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.071m	2.824ms	1	1	100.00
		chip_sw_csrng_smoketest	2.077m	2.865ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.985m	6.784ms	1	1	100.00
		chip_sw_gpio_smoketest	3.315m	2.745ms	1	1	100.00
		chip_sw_hmac_smoketest	3.052m	3.275ms	1	1	100.00
		chip_sw_kmac_smoketest	3.575m	3.444ms	1	1	100.00
		chip_sw_otbn_smoketest	19.270m	9.892ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.475m	4.957ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.500m	5.975ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.179m	2.076ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.984m	3.318ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.284m	2.758ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.850m	2.799ms	1	1	100.00
		chip_sw_uart_smoketest	1.831m	2.779ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.537m	2.622ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.541m	5.201ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.243h	61.680ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.812m	14.698ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.311m	4.471ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.663m	2.905ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.839m	2.798ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.020h	53.964ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.068h	56.917ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.910s	2.811ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.910s	2.811ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.348h	33.446ms	1	1	100.00
		chip_same_csr_outstanding	21.612m	15.856ms	1	1	100.00
		chip_csr_hw_reset	2.496m	4.679ms	1	1	100.00
		chip_csr_rw	3.069m	3.963ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.348h	33.446ms	1	1	100.00
		chip_same_csr_outstanding	21.612m	15.856ms	1	1	100.00
		chip_csr_hw_reset	2.496m	4.679ms	1	1	100.00
		chip_csr_rw	3.069m	3.963ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	33.260s	546.635us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.510s	51.368us	1	1	100.00
		xbar_smoke_large_delays	38.340s	6.341ms	1	1	100.00
		xbar_smoke_slow_rsp	46.090s	5.294ms	1	1	100.00
		xbar_random_zero_delays	16.840s	316.504us	1	1	100.00
		xbar_random_large_delays	5.203m	53.435ms	1	1	100.00
		xbar_random_slow_rsp	2.260m	15.250ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.550s	536.445us	1	1	100.00
		xbar_error_and_unmapped_addr	20.930s	303.337us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	18.880s	375.132us	1	1	100.00
		xbar_error_and_unmapped_addr	20.930s	303.337us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	27.590s	1.403ms	1	1	100.00
		xbar_access_same_device_slow_rsp	4.937m	34.239ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.930s	1.116ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	13.950s	145.198us	1	1	100.00
		xbar_stress_all_with_error	3.081m	8.619ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.010m	350.676us	1	1	100.00
		xbar_stress_all_with_reset_error	2.508m	497.506us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.812m	14.698ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	39.235m	30.407ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.589m	15.001ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.274m	11.494ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.855m	15.584ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.668m	16.337ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.540m	16.656ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	43.553m	16.939ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.760s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.620s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.340s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.220s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.990s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	23.550s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	20.260s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.120s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.510s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.990s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.480s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.590s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.990s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.080s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.990s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.580s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.480s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.700s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.890s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.760s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.490s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.490s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.230s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.210s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.420s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.736m	11.072ms	1	1	100.00
		rom_e2e_asm_init_dev	41.911m	16.267ms	1	1	100.00
		rom_e2e_asm_init_prod	42.131m	16.066ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.112m	18.280ms	1	1	100.00
		rom_e2e_asm_init_rma	40.518m	19.650ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.813m	14.968ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.140m	18.012ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.722m	14.855ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.148m	16.020ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.011m	34.852ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.011m	34.852ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.579m	2.927ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.965m	2.783ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.838m	3.033ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.754m	3.495ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	22.008m	10.074ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.408m	2.791ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.034m	5.742ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.773m	5.309ms	1	1	100.00
		chip_plic_all_irqs_10	4.806m	4.110ms	1	1	100.00
		chip_plic_all_irqs_20	5.577m	4.287ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.887m	3.329ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.967m	10.787ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.399m	3.475ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.856m	2.785ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.430m	10.551ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	8.563m	5.643ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.300m	7.127ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.055m	7.914ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.991h	255.476ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.584m	4.659ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.475m	4.957ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.584m	4.659ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.515m	7.750ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.515m	7.750ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.639m	6.602ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.486m	4.571ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.958m	5.945ms	1	1	100.00
		chip_sw_aes_idle	2.754m	3.495ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.689m	2.495ms	1	1	100.00
		chip_sw_kmac_idle	2.539m	3.332ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.611m	4.491ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.695m	5.443ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.431m	3.975ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.594m	4.412ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.793m	9.583ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.214m	4.162ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.242m	4.653ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.722m	4.020ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.710m	4.608ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.388m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.445m	4.846ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.923m	7.948ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.528m	6.711ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.722m	4.020ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.710m	4.608ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.175m	4.718ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.313m	5.067ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.722m	18.590ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.965m	2.783ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.111m	6.516ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.726m	3.226ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.114m	11.886ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.784m	3.361ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.423m	5.346ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.162m	2.754ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.852m	2.073ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.882m	4.321ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.881m	6.884ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.702m	25.239ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.970m	3.522ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.802m	3.158ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.800m	10.065ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.031m	2.602ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.593m	5.389ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.762m	18.346ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.573h	156.567ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.923m	7.948ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.848m	4.604ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.964m	3.400ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	8.563m	5.643ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.145m	6.050ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.583m	4.428ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.623m	4.780ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.517m	2.727ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	37.067m	13.349ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.562m	2.269ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.635m	6.557ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.562m	2.269ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.145m	6.050ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.465m	3.104ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.793m	19.023ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.467m	5.433ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.313m	5.067ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.296m	3.468ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.175m	4.718ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.306m	42.779ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.793m	19.023ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.705m	3.019ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.306m	42.779ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.669m	4.613ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.238m	4.990ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.821m	6.154ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.821m	6.154ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.650m	3.527ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.726m	3.226ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.689m	2.495ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.441m	3.350ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.027m	3.417ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.591m	5.245ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.500m	5.436ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.322m	5.025ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.008m	3.805ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.114m	11.886ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.865m	10.504ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	22.008m	10.074ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	33.382m	10.928ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.651m	2.229ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.067m	3.185ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.784m	3.361ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.515m	2.215ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	19.140m	8.174ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.539m	3.332ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.034m	5.742ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.193m	4.591ms	1	1	100.00
		chip_tap_straps_rma	6.614m	6.517ms	1	1	100.00
		chip_tap_straps_prod	17.330m	15.547ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.673m	3.674ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.977m	7.139ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.144m	4.124ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.306m	42.779ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.665m	3.283ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.008m	7.509ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.075m	7.503ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.445m	5.889ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.521m	9.055ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.867m	6.966ms	1	1	100.00
		chip_prim_tl_access	1.669m	4.613ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.528m	6.711ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.214m	4.162ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.242m	4.653ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.722m	4.020ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.710m	4.608ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.388m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.445m	4.846ms	1	1	100.00
		chip_tap_straps_dev	3.193m	4.591ms	1	1	100.00
		chip_tap_straps_rma	6.614m	6.517ms	1	1	100.00
		chip_tap_straps_prod	17.330m	15.547ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.898m	10.602ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.842m	3.827ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.669m	3.447ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.416m	3.817ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.376m	3.859ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.905m	25.091ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.898m	10.602ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.176h	47.042ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.059h	46.381ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.332m	8.663ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.056h	46.409ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.905m	25.091ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.560m	2.793ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.247m	2.309ms	1	1	100.00
		rom_volatile_raw_unlock	1.297m	2.743ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.519m	16.332ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.722m	18.590ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.958m	5.945ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.958m	5.945ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.958m	5.945ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.863m	3.672ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.793m	19.023ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.863m	3.672ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.253m	4.195ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.634ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.793m	19.023ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.863m	3.672ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.752m	11.923ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.253m	4.195ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.634ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.827m	5.493ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.673m	3.674ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.665m	3.283ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.008m	7.509ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.075m	7.503ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.445m	5.889ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.094m	13.777ms	1	1	100.00
		chip_prim_tl_access	1.669m	4.613ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.669m	4.613ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.087m	8.770ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.879m	6.674ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.696m	23.855ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.159m	7.685ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.008m	7.563ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.499m	5.873ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.001m	22.946ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.671m	17.438ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.515m	7.750ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.296m	10.489ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.030m	5.348ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.879m	6.674ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.622m	4.054ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.763m	45.760ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.948m	5.588ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.767m	6.872ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.441m	20.797ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.053m	8.383ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.982m	13.361ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.896m	22.865ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.018m	3.046ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.521m	9.055ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.521m	9.055ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.982m	13.361ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.441m	20.797ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.030m	5.348ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.475m	4.957ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.070m	3.465ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.382m	3.886ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.133m	4.790ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.967m	10.787ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.551m	2.931ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.300m	7.127ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.841m	4.984ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.972m	5.284ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.312m	3.173ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.634ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.382m	3.886ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.382m	3.886ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	21.597m	18.249ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.563m	13.589ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.070m	3.465ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.573m	5.860ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.503m	6.298ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.614m	6.517ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.898m	10.602ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.773m	5.309ms	1	1	100.00
		chip_plic_all_irqs_10	4.806m	4.110ms	1	1	100.00
		chip_plic_all_irqs_20	5.577m	4.287ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.684m	2.816ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.011m	2.704ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.812m	14.698ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.802m	8.234ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.284m	3.634ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.735m	3.837ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.584m	3.142ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.253m	4.195ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.423m	5.346ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.581m	7.392ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.075m	7.467ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.867m	6.966ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.591m	5.841ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.053m	8.383ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.594m	22.588ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.090m	2.540ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.344m	4.185ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.166m	4.337ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.594m	22.588ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.594m	22.588ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.484m	10.957ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.484m	10.957ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.373m	6.319ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.011m	34.852ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.468m	3.267ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.228m	3.030ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.343m	3.412ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.847m	3.920ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.932m	8.309ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.377h	31.706ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.414m	12.120ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.057m	3.197ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.812m	3.497ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.316m	3.213ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.550h	72.017ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.116m	3.940ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	8.549m	14.841ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.852m	11.906ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.949m	13.055ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.698m	3.795ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.968m	5.240ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.043m	5.068ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.328s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.841m	5.083ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.734m	2.599ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.460m	6.949ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.919m	6.363ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.606m	2.116ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.876m	4.710ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.181m	2.527ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.656m	5.541ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.968m	5.765ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.404m	3.480ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.982m	13.361ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	8.549m	14.841ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.852m	11.906ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.949m	13.055ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.749m	5.487ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.640m	5.323ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.551h	38.372ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.551h	38.372ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.246m	3.465ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.525m	3.998ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.559m	19.540ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.743m	3.559ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.132m	5.357ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.806m	2.441ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.184m	3.252ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.295m	3.338ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.148s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.717m	3.389ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.58633357546227990018121917381476114980878114861117679107167725778382088935871
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.74761945502237846209995091124470991395940815409917421878784625677061631081730
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.67084328344594192637980273855485972932965175490930019561010700053442674743226
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.28700506871562408961741268523620068553625763196349584978197875844208686814468
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.27735445395884963947398346038111105899356003807930008498414330343897913806327
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.37882404247376297903782275357637985444129798059307061161237706726589469370374
    Line 484, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.13013628402042735974394894362518581442157441323137598429261550411844001988060
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.82704309720294360591940897400152450924970621700036169286307975187246077834780
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.27930181389281119199429437259785638829044467514842252445710106544581747128794
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.96033365619906513022261224659104803948083607506454765870481051075298979499620
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.104809011206007448615101798580846638187293321253998925908378729423942441748842
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.83761349922221071080176330849659198232603802957668131779473037505877862755420
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.81825317380024129426421907899681642135606463247110785788395659205893566786717
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.29622391736587191923866653996690462678578463211340417853373858227244384740820
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.165s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.103538803467690594401845584728142638043512657103538519274762512650674438719242
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.159s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.52069606525973363509276934981980983463294919931430191902576879826786296584728
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.81887754130493854517764083682868652934072522708321221614234563227132133652813
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.51336085247521494575139189237096497079639187167537741121195470761220427959005
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.96894472693037796411250772950758981266149113764032338548002441360602435336074
    Line 484, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.66479114359997879710577513723925606387280108201082910458893322325236252120923
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3633.947300 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3633.947300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80971) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.80759844794034592118268250119935710953657974686033176604029976085765556282346
Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3886.315370 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80971) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3886.315370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.20026205375095296881942641406562493439991164964397973074935260912325778973194
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10957.305944 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10957.305944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.40886368331173253091098137007572355207717992051906042880829106095490110927196
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34851.661657 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34851.661657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.37869591679267362563912173707048926368878066020096666869783904084649272269311
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2791.423320 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2791.423320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.7403090238304568439436806998616947290538657926134092619176044707824823610580
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2784.577964 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2784.577964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.45776960283780696901278367773789125668681020619672812692104923865493515637894
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3350.081144 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3350.081144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38901) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.47419984467412753295028823324504272323325117762220067438572082520245128022645
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2811.490116 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38901) { a_addr: 'h107ac  a_data: 'h9fd244b1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h1a9b8  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2811.490116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.76751647698269394785101444538341870820449460778284208674170210992113224272181
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2904.980000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2904.980000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.92499882099872931059715769080013517664153732584092411806127248930564594847356
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2797.850000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2797.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.84086483385620490890023524023467559369836366423339049829118256245387931658966
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20575.389352 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20575.389352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.94030113931673242820540839981852452860893757700715944913812741276022444497337
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3940.141735 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3940.141735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.21295680320672002379483236108941084584588857451624149097195950756858600118208
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.62930627426558008477708295682083980604622893641587774409481788306094737175499
    Line 565, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.14756970246084156779214618833938972974803068596434926540757951674526119215640
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 14840.915074 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14840.915074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32127) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1631873458611605882866726632926487365041741338583730529197695418545908115292
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2812.179080 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32127) { a_addr: 'h106e0  a_data: 'h60476717  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h19e0c  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2812.179080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---