ADC_CTRL Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 0 1 0.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 0 1 0.00
V1 csr_rw adc_ctrl_csr_rw 0 1 0.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 0 1 0.00
V1 csr_aliasing adc_ctrl_csr_aliasing 0 1 0.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 0 1 0.00
adc_ctrl_csr_aliasing 0 1 0.00
V1 TOTAL 0 6 0.00
V2 filters_polled adc_ctrl_filters_polled 0 1 0.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 0 1 0.00
V2 filters_interrupt adc_ctrl_filters_interrupt 0 1 0.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 0 1 0.00
V2 filters_wakeup adc_ctrl_filters_wakeup 0 1 0.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 0 1 0.00
V2 filters_both adc_ctrl_filters_both 0 1 0.00
V2 clock_gating adc_ctrl_clock_gating 0 1 0.00
V2 poweron_counter adc_ctrl_poweron_counter 0 1 0.00
V2 lowpower_counter adc_ctrl_lowpower_counter 0 1 0.00
V2 fsm_reset adc_ctrl_fsm_reset 0 1 0.00
V2 stress_all adc_ctrl_stress_all 0 1 0.00
V2 alert_test adc_ctrl_alert_test 0 1 0.00
V2 intr_test adc_ctrl_intr_test 0 1 0.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 0 1 0.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 0 1 0.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 0 1 0.00
adc_ctrl_csr_rw 0 1 0.00
adc_ctrl_csr_aliasing 0 1 0.00
adc_ctrl_same_csr_outstanding 0 1 0.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 0 1 0.00
adc_ctrl_csr_rw 0 1 0.00
adc_ctrl_csr_aliasing 0 1 0.00
adc_ctrl_same_csr_outstanding 0 1 0.00
V2 TOTAL 0 16 0.00
V2S tl_intg_err adc_ctrl_sec_cm 0 1 0.00
adc_ctrl_tl_intg_err 0 1 0.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 0 1 0.00
V2S TOTAL 0 2 0.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 25 0.00

Failure Buckets