f6ac363| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0.810s | 48.788us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 1 | 0.00 | ||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | firmware | edn_genbits | 1.100s | 121.614us | 1 | 1 | 100.00 |
| V2 | csrng_commands | edn_genbits | 1.100s | 121.614us | 1 | 1 | 100.00 |
| V2 | genbits | edn_genbits | 1.100s | 121.614us | 1 | 1 | 100.00 |
| V2 | interrupts | edn_intr | 18.382s | 0 | 1 | 0.00 | |
| V2 | alerts | edn_alert | 0.960s | 49.801us | 1 | 1 | 100.00 |
| V2 | errs | edn_err | 0.760s | 25.406us | 1 | 1 | 100.00 |
| V2 | disable | edn_disable | 0.750s | 20.853us | 1 | 1 | 100.00 |
| edn_disable_auto_req_mode | 0.790s | 288.846us | 1 | 1 | 100.00 | ||
| V2 | stress_all | edn_stress_all | 1.440s | 80.507us | 1 | 1 | 100.00 |
| V2 | intr_test | edn_intr_test | 0 | 1 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0.700s | 125.003us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| edn_csr_rw | 0 | 1 | 0.00 | ||||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 1 | 0.00 | ||
| edn_csr_rw | 0 | 1 | 0.00 | ||||
| edn_csr_aliasing | 0 | 1 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 7 | 11 | 63.64 | |||
| V2S | tl_intg_err | edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 |
| edn_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 19.985s | 0 | 1 | 0.00 | |
| V2S | sec_cm_config_mubi | edn_alert | 0.960s | 49.801us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0.960s | 49.801us | 1 | 1 | 100.00 |
| edn_sec_cm | 5.780s | 1.019ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0.960s | 49.801us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 3 | 33.33 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 51.850s | 13.990ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 10 | 21 | 47.62 |
Job killed most likely because its dependent job failed. has 9 failures:
Test edn_tl_errors has 1 failures.
Test edn_tl_intg_err has 1 failures.
Test edn_intr_test has 1 failures.
Test edn_csr_hw_reset has 1 failures.
Test edn_csr_rw has 1 failures.
... and 4 more tests.
Job returned non-zero exit code has 2 failures:
Test edn_regwen has 1 failures.
0.edn_regwen.77526437468383944789958636289299408282395028606787399458342569932249777166898
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_regwen/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:27 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test edn_intr has 1 failures.
0.edn_intr.26678777606965983729283748815669891007932820108860228023217928047841001776600
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_intr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:27 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes