HMAC Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	5.490s	598.552us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.690s	37.284us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.620s	92.103us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.030s	1.603ms	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.080s	109.675us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	0.770s	61.607us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.620s	92.103us	1	1	100.00
		hmac_csr_aliasing	2.080s	109.675us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	19.637s		0	1	0.00
V2	back_pressure	hmac_back_pressure	38.860s	1.083ms	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.016m	28.121ms	1	1	100.00
		hmac_test_sha384_vectors	6.022m	60.630ms	1	1	100.00
		hmac_test_sha512_vectors	18.200s	913.908us	1	1	100.00
		hmac_test_hmac256_vectors	5.520s	368.757us	1	1	100.00
		hmac_test_hmac384_vectors	7.950s	290.608us	1	1	100.00
		hmac_test_hmac512_vectors	8.660s	278.399us	1	1	100.00
V2	burst_wr	hmac_burst_wr	2.400s	345.173us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	6.401m	3.810ms	1	1	100.00
V2	error	hmac_error	59.340s	21.551ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	41.660s	5.522ms	1	1	100.00
V2	save_and_restore	hmac_smoke	5.490s	598.552us	1	1	100.00
		hmac_long_msg	19.637s		0	1	0.00
		hmac_back_pressure	38.860s	1.083ms	1	1	100.00
		hmac_datapath_stress	6.401m	3.810ms	1	1	100.00
		hmac_burst_wr	2.400s	345.173us	1	1	100.00
		hmac_stress_all	6.605m	6.685ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	5.490s	598.552us	1	1	100.00
		hmac_long_msg	19.637s		0	1	0.00
		hmac_back_pressure	38.860s	1.083ms	1	1	100.00
		hmac_datapath_stress	6.401m	3.810ms	1	1	100.00
		hmac_wipe_secret	41.660s	5.522ms	1	1	100.00
		hmac_test_sha256_vectors	3.016m	28.121ms	1	1	100.00
		hmac_test_sha384_vectors	6.022m	60.630ms	1	1	100.00
		hmac_test_sha512_vectors	18.200s	913.908us	1	1	100.00
		hmac_test_hmac256_vectors	5.520s	368.757us	1	1	100.00
		hmac_test_hmac384_vectors	7.950s	290.608us	1	1	100.00
		hmac_test_hmac512_vectors	8.660s	278.399us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	5.490s	598.552us	1	1	100.00
		hmac_long_msg	19.637s		0	1	0.00
		hmac_back_pressure	38.860s	1.083ms	1	1	100.00
		hmac_datapath_stress	6.401m	3.810ms	1	1	100.00
		hmac_burst_wr	2.400s	345.173us	1	1	100.00
		hmac_error	59.340s	21.551ms	1	1	100.00
		hmac_wipe_secret	41.660s	5.522ms	1	1	100.00
		hmac_test_sha256_vectors	3.016m	28.121ms	1	1	100.00
		hmac_test_sha384_vectors	6.022m	60.630ms	1	1	100.00
		hmac_test_sha512_vectors	18.200s	913.908us	1	1	100.00
		hmac_test_hmac256_vectors	5.520s	368.757us	1	1	100.00
		hmac_test_hmac384_vectors	7.950s	290.608us	1	1	100.00
		hmac_test_hmac512_vectors	8.660s	278.399us	1	1	100.00
		hmac_stress_all	6.605m	6.685ms	1	1	100.00
V2	stress_all	hmac_stress_all	6.605m	6.685ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.580s	14.719us	1	1	100.00
V2	intr_test	hmac_intr_test	0.580s	56.910us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.920s	413.348us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.920s	413.348us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.690s	37.284us	1	1	100.00
		hmac_csr_rw	0.620s	92.103us	1	1	100.00
		hmac_csr_aliasing	2.080s	109.675us	1	1	100.00
		hmac_same_csr_outstanding	1.320s	301.539us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.690s	37.284us	1	1	100.00
		hmac_csr_rw	0.620s	92.103us	1	1	100.00
		hmac_csr_aliasing	2.080s	109.675us	1	1	100.00
		hmac_same_csr_outstanding	1.320s	301.539us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	tl_intg_err	hmac_sec_cm	0.830s	175.505us	1	1	100.00
		hmac_tl_intg_err	3.250s	1.883ms	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.250s	1.883ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	5.490s	598.552us	1	1	100.00
V3	stress_reset	hmac_stress_reset	2.610s	1.610ms	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.550m	8.837ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	0.740s	29.286us	1	1	100.00
		TOTAL			27	28	96.43

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac_long_msg has 1 failures.

    • 0.hmac_long_msg.84720187915765651031893580706577553165140156238124750817923756824559306360849
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_long_msg/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:23 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255