f6ac363| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 23.780s | 36.606ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 16.480s | 831.324us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.720s | 69.483us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.660s | 20.922us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.080s | 477.430us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.360s | 407.408us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.870s | 243.110us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.660s | 20.922us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.360s | 407.408us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.870s | 159.183us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 2.828m | 19.684ms | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 16.630s | 27.963ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.620s | 16.055us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 39.980s | 21.667ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 24.360s | 3.221ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.810s | 85.864us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 4.710s | 328.982us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 4.680s | 156.175us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 43.940s | 2.952ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 24.940s | 3.311ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.240s | 250.516us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 2.030s | 1.105ms | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 20.306s | 0 | 1 | 0.00 | |
| V2 | target_maxperf | i2c_target_perf | 4.760s | 1.103ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 12.790s | 448.791us | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 2.990s | 881.625us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.930s | 184.242us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 0.730s | 264.658us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 1.693m | 46.633ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 12.790s | 448.791us | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 20.157s | 0 | 1 | 0.00 | |||
| V2 | target_timeout | i2c_target_timeout | 4.570s | 5.577ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 13.180s | 1.642ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 1.880s | 1.270ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 24.791s | 0 | 1 | 0.00 | |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.670s | 1.506ms | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.630s | 135.936us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 16.630s | 27.963ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 1.010s | 89.183us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 24.940s | 3.311ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 1.590s | 152.940us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.890s | 566.317us | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.850s | 595.228us | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 0.980s | 241.006us | 0 | 1 | 0.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 5.420s | 2.334ms | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.430s | 825.045us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.610s | 19.304us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.610s | 90.986us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.390s | 286.212us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.390s | 286.212us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.720s | 69.483us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.660s | 20.922us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.360s | 407.408us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.750s | 109.641us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.720s | 69.483us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.660s | 20.922us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.360s | 407.408us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.750s | 109.641us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 30 | 38 | 78.95 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.150s | 284.788us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.870s | 768.553us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.150s | 284.788us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 12.330s | 667.232us | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 0.920s | 624.943us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 22.490s | 3.698ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 39 | 50 | 78.00 |
Job returned non-zero exit code has 3 failures:
Test i2c_target_intr_stress_wr has 1 failures.
0.i2c_target_intr_stress_wr.87136252809316937051605492923339486225284767717785533732645207679690862102338
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_stress_all has 1 failures.
0.i2c_target_stress_all.25851716696447607169382526355763625209571705689475160538422068158000861971481
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:37 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_hrst has 1 failures.
0.i2c_target_hrst.103446153826709689953767480742022863935170460033242741594311250660792195921907
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:37 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:
Test i2c_host_error_intr has 1 failures.
0.i2c_host_error_intr.79370653801582913744533331715968870821563957103565589754423380016500641693979
Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 159182848 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 159182848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
0.i2c_host_stress_all.56703771207830288665433906569570627708169155765171705706867671437070729846535
Line 105, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 19683681944 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 19683681944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.9210447439308556440590961543102757089253181468606950096928998609110845672956
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 667232384 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 667232384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.17910586791415694783493489184645027021649058630538102238746850983239954847230
Line 108, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3698078053 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3698078053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.38345746088890430853355464118158275716856350605404969621878407561133165138711
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1104634934 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1104634934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
0.i2c_target_unexp_stop.91665799037816509090035265483532467339824600114144621155771484558980386380944
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 624942972 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 624942972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
0.i2c_host_mode_toggle.112258380914916266773328747811075254845914220685666670373643148941897656010144
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 250515579 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
0.i2c_target_nack_txstretch.45177260120417015564273623879746043434624493768022888787408473095087321100688
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 241005788 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 241005788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---