KEYMGR Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.850s	232.540us	1	1	100.00
V1	random	keymgr_random	4.170s	864.300us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.880s	106.168us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.920s	35.597us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.870s	14.279ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.830s	2.096ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.540s	186.377us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.920s	35.597us	1	1	100.00
		keymgr_csr_aliasing	5.830s	2.096ms	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	7.150s	223.547us	1	1	100.00
V2	sideload	keymgr_sideload	1.590s	147.697us	1	1	100.00
		keymgr_sideload_kmac	4.500s	568.171us	1	1	100.00
		keymgr_sideload_aes	25.940s	2.691ms	1	1	100.00
		keymgr_sideload_otbn	5.090s	2.830ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.000s	28.267us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.560s	107.596us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.630s	55.969us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	22.294s		0	1	0.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.850s	949.907us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	4.560s	392.639us	1	1	100.00
V2	stress_all	keymgr_stress_all	31.860s	1.981ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.730s	11.124us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.750s	61.439us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.990s	471.986us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.990s	471.986us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.880s	106.168us	1	1	100.00
		keymgr_csr_rw	0.920s	35.597us	1	1	100.00
		keymgr_csr_aliasing	5.830s	2.096ms	1	1	100.00
		keymgr_same_csr_outstanding	1.160s	217.726us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.880s	106.168us	1	1	100.00
		keymgr_csr_rw	0.920s	35.597us	1	1	100.00
		keymgr_csr_aliasing	5.830s	2.096ms	1	1	100.00
		keymgr_same_csr_outstanding	1.160s	217.726us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
		keymgr_tl_intg_err	5.590s	218.642us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.380s	84.896us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.380s	84.896us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.380s	84.896us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.380s	84.896us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.900s	341.363us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.590s	218.642us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.380s	84.896us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	7.150s	223.547us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.170s	864.300us	1	1	100.00
		keymgr_csr_rw	0.920s	35.597us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.170s	864.300us	1	1	100.00
		keymgr_csr_rw	0.920s	35.597us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.170s	864.300us	1	1	100.00
		keymgr_csr_rw	0.920s	35.597us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.560s	107.596us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.850s	949.907us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.850s	949.907us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.170s	864.300us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.760s	354.620us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.930s	104.502us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.560s	107.596us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.930s	104.502us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.930s	104.502us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.930s	104.502us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.240s	1.126ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.930s	104.502us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.170s	1.188ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test keymgr_sw_invalid_input has 1 failures.

    • 0.keymgr_sw_invalid_input.20296428689922123008127741997560567815814390570760176049486465655643840446235
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:25 2025
        Feature removed during lmreread, or wrong
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        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255