KMAC/MASKED Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.550s	2.115ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	16.253s		0	1	0.00
V1	csr_rw	kmac_csr_rw	0.860s	46.754us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.040s	1.185ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	2.890s	81.606us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.860s	81.290us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.860s	46.754us	1	1	100.00
		kmac_csr_aliasing	2.890s	81.606us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.660s	48.797us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.010s	34.821us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	long_msg_and_output	kmac_long_msg_and_output	2.200m	2.048ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.501m	5.609ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.672m	828.438ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.923m	251.392ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.840s	8.043ms	1	1	100.00
		kmac_test_vectors_sha3_512	0.800s	46.033us	0	1	0.00
		kmac_test_vectors_shake_128	2.337m	34.235ms	1	1	100.00
		kmac_test_vectors_shake_256	1.621m	14.301ms	1	1	100.00
		kmac_test_vectors_kmac	1.690s	173.866us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.620s	32.294us	1	1	100.00
V2	sideload	kmac_sideload	4.006m	10.718ms	1	1	100.00
V2	app	kmac_app	2.444m	17.291ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	39.380s	1.220ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.236m	50.928ms	1	1	100.00
V2	error	kmac_error	4.254m	68.517ms	1	1	100.00
V2	key_error	kmac_key_error	1.580s	1.096ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.740s	363.307us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	0.810s	47.802us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.900s	1.380ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	54.800s	29.846ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.070s	57.067us	1	1	100.00
V2	stress_all	kmac_stress_all	16.923m	18.825ms	1	1	100.00
V2	intr_test	kmac_intr_test	16.347s		0	1	0.00
V2	alert_test	kmac_alert_test	0.720s	90.872us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.530s	82.269us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.530s	82.269us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	16.253s		0	1	0.00
		kmac_csr_rw	0.860s	46.754us	1	1	100.00
		kmac_csr_aliasing	2.890s	81.606us	1	1	100.00
		kmac_same_csr_outstanding	1.220s	99.262us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	16.253s		0	1	0.00
		kmac_csr_rw	0.860s	46.754us	1	1	100.00
		kmac_csr_aliasing	2.890s	81.606us	1	1	100.00
		kmac_same_csr_outstanding	1.220s	99.262us	1	1	100.00
V2		TOTAL			24	26	92.31
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	59.437us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	59.437us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	59.437us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	59.437us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.110s	137.370us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.101m	14.299ms	1	1	100.00
		kmac_tl_intg_err	3.360s	1.185ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.360s	1.185ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.070s	57.067us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.550s	2.115ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.006m	10.718ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	59.437us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.101m	14.299ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.101m	14.299ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.101m	14.299ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.550s	2.115ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.070s	57.067us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.101m	14.299ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.567m	2.073ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.550s	2.115ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.860s	3.394ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			37	40	92.50

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test kmac_intr_test has 1 failures.

    • 0.kmac_intr_test.54483776163557277565068724858676840519289380337654202742204829533471168894599
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_intr_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:32 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_csr_hw_reset has 1 failures.

    • 0.kmac_csr_hw_reset.17673524043541861573519288792584010828060201036753637172560964692119971255851
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:32 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_512 has 1 failures.

    • 0.kmac_test_vectors_sha3_512.19308328060258255281478993970168820055842418596625083036470917786628106578384
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log

        UVM_ERROR @  46032715 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  46032715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---