f6ac363| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 30.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 37.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | pattgen_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 25.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 1.000s | 35.999us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 39.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| pattgen_csr_aliasing | 1.000s | 35.999us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | perf | pattgen_perf | 29.000s | 0 | 1 | 0.00 | |
| V2 | cnt_rollover | cnt_rollover | 18.000s | 0 | 1 | 0.00 | |
| V2 | error | pattgen_error | 1.000s | 133.810us | 1 | 1 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 12.000s | 1.481ms | 1 | 1 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 29.000s | 0 | 1 | 0.00 | |
| V2 | intr_test | pattgen_intr_test | 29.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 21.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 21.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 37.000s | 0 | 1 | 0.00 | |
| pattgen_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 1.000s | 35.999us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 25.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 37.000s | 0 | 1 | 0.00 | |
| pattgen_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 1.000s | 35.999us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 25.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 2 | 8 | 25.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 22.000s | 0 | 1 | 0.00 | |
| pattgen_sec_cm | 1.000s | 43.099us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 22.000s | 0 | 1 | 0.00 | |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 21.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 25.000s | 0 | 1 | 0.00 | ||
| TOTAL | 4 | 18 | 22.22 |
Job returned non-zero exit code has 14 failures:
Test pattgen_smoke has 1 failures.
0.pattgen_smoke.101239179991882995407856514045948995569696317473108802274922986191680685190637
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 20:28:40 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_perf has 1 failures.
0.pattgen_perf.24417097705212620941108920069545832986434088264828142462274384932915088261736
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 20:28:40 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test cnt_rollover has 1 failures.
0.cnt_rollover.23426338382452016949489918243558630897202884900874762388951950322167088357896
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 20:28:30 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_inactive_level has 1 failures.
0.pattgen_inactive_level.82171596220299691609235985938828786464994990465190797451603496489922665405977
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 20:28:38 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_tl_errors has 1 failures.
0.pattgen_tl_errors.30197596694904194041840301806102185529270483827153594000158939917308381289867
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_tl_errors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 20:28:42 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 9 more tests.