ROM_CTRL/32KB Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.600s 178.300us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.790s 173.358us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.820s 183.795us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.940s 167.928us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.330s 556.139us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.770s 607.413us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.820s 183.795us 1 1 100.00
rom_ctrl_csr_aliasing 3.330s 556.139us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.000s 210.488us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.840s 172.604us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.610s 181.179us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.940s 588.223us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.010s 0 1 0.00
V2 alert_test rom_ctrl_alert_test 3.890s 171.810us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.570s 215.802us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.570s 215.802us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.790s 173.358us 1 1 100.00
rom_ctrl_csr_rw 3.820s 183.795us 1 1 100.00
rom_ctrl_csr_aliasing 3.330s 556.139us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.030s 212.002us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.790s 173.358us 1 1 100.00
rom_ctrl_csr_rw 3.820s 183.795us 1 1 100.00
rom_ctrl_csr_aliasing 3.330s 556.139us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.030s 212.002us 1 1 100.00
V2 TOTAL 5 6 83.33
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 10.610s 5.070ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
rom_ctrl_tl_intg_err 13.897s 0 1 0.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
V2S prim_count_check rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.600s 178.300us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.600s 178.300us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.600s 178.300us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 13.897s 0 1 0.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.010s 0 1 0.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 38.790s 1.086ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 10.610s 5.070ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.035m 1.768ms 0 1 0.00
V2S TOTAL 2 4 50.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 48.740s 8.528ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 16 19 84.21

Failure Buckets