ROM_CTRL/64KB Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	20.369s		0	1	0.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.890s	306.310us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.520s	3.990ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.910s	297.336us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.850s	297.969us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.440s	1.913ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.520s	3.990ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.850s	297.969us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.880s	299.814us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.430s	336.253us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.310s	591.654us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	29.030s	1.071ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.010s	2.104ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	5.590s	673.642us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.800s	3.118ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.800s	3.118ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.890s	306.310us	1	1	100.00
		rom_ctrl_csr_rw	8.520s	3.990ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.850s	297.969us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.900s	290.077us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.890s	306.310us	1	1	100.00
		rom_ctrl_csr_rw	8.520s	3.990ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.850s	297.969us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.900s	290.077us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	25.570s	1.108ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
		rom_ctrl_tl_intg_err	1.536m	903.180us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	20.369s		0	1	0.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	20.369s		0	1	0.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	20.369s		0	1	0.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.536m	903.180us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
		rom_ctrl_kmac_err_chk	13.010s	2.104ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.529m	20.687ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	25.570s	1.108ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.572m	721.457us	1	1	100.00
V2S		TOTAL			4	4	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.151m	88.168ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test rom_ctrl_smoke has 1 failures.

    • 0.rom_ctrl_smoke.59478222571678687002763668681465276828050979222886746992188191231038680285061
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:38 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255