f6ac363| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.530s | 45.374us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.530s | 20.050us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 13.860s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.670s | 102.760us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.150s | 54.818us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.530s | 20.050us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.670s | 102.760us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 4 | 6 | 66.67 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 1 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 1 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 1 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 1 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | rv_timer_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 0.580s | 14.996us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.330s | 64.230us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.330s | 64.230us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.530s | 45.374us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.530s | 20.050us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.670s | 102.760us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.650s | 17.635us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.530s | 45.374us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.530s | 20.050us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.670s | 102.760us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.650s | 17.635us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 8 | 37.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 1 | 0.00 | ||
| rv_timer_tl_intg_err | 0.730s | 164.198us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.730s | 164.198us | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | min_value | rv_timer_min | 0 | 1 | 0.00 | ||
| V3 | max_value | rv_timer_max | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 8 | 19 | 42.11 |
Job killed most likely because its dependent job failed. has 10 failures:
Test rv_timer_random has 1 failures.
Test rv_timer_min has 1 failures.
Test rv_timer_max has 1 failures.
Test rv_timer_disabled has 1 failures.
Test rv_timer_cfg_update_on_fly has 1 failures.
... and 5 more tests.
Job returned non-zero exit code has 2 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/default/build.log
recompiling module tb
All of 69 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 12.571 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test rv_timer_csr_bit_bash has 1 failures.
0.rv_timer_csr_bit_bash.83540040390556432613770606600293606933933028721777736977453687506822820020887
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 16 20:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255