SPI_DEVICE/1R1W Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.658m	45.527ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.080s	42.310us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.420s	126.931us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.830s	668.227us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.270s	2.538ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.550s	523.853us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.420s	126.931us	1	1	100.00
		spi_device_csr_aliasing	10.270s	2.538ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.640s	12.901us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.040s	401.826us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.710s	95.094us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.690s	3.272us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	5.698us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.960s	623.866us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.960s	623.866us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.019s		0	1	0.00
		spi_device_tpm_sts_read	0.670s	23.495us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.260s	4.251ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.130s	831.942us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.480s	830.239us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.480s	830.239us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.040s	491.385us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.040s	491.385us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.040s	491.385us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.040s	491.385us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.040s	491.385us	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.830s	2.724ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	31.190s	4.461ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	31.190s	4.461ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	31.190s	4.461ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.000s	729.700us	1	1	100.00
		spi_device_read_buffer_direct	2.970s	391.392us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	31.190s	4.461ms	1	1	100.00
		spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.213m	64.131ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.920s	1.827ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.920s	1.827ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.658m	45.527ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.620s	7.347ms	1	1	100.00
V2	stress_all	spi_device_stress_all	46.350s	9.783ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.650s	14.870us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	17.522us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.000s	245.532us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.000s	245.532us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.080s	42.310us	1	1	100.00
		spi_device_csr_rw	1.420s	126.931us	1	1	100.00
		spi_device_csr_aliasing	10.270s	2.538ms	1	1	100.00
		spi_device_same_csr_outstanding	3.070s	210.171us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.080s	42.310us	1	1	100.00
		spi_device_csr_rw	1.420s	126.931us	1	1	100.00
		spi_device_csr_aliasing	10.270s	2.538ms	1	1	100.00
		spi_device_same_csr_outstanding	3.070s	210.171us	1	1	100.00
V2		TOTAL			19	22	86.36
V2S	tl_intg_err	spi_device_sec_cm	1.000s	107.017us	1	1	100.00
		spi_device_tl_intg_err	11.620s	593.436us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.620s	593.436us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds			0	1	0.00
		TOTAL			29	33	87.88

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.95076122147790661067797473248359676670756871379105097143912303405809021843482
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2843306 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[101])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2843306 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2843306 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[997])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.32636542475060161998891525693553334128732239459902435071162802326505296585229
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3337120 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd6131d [110101100001001100011101] vs 0x0 [0])
        UVM_ERROR @   3433120 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9d05d1 [100111010000010111010001] vs 0x0 [0])
        UVM_ERROR @   3478120 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18b120 [110001011000100100000] vs 0x0 [0])
        UVM_ERROR @   3483120 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb8514 [101110111000010100010100] vs 0x0 [0])
        UVM_ERROR @   3559120 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdfc8e3 [110111111100100011100011] vs 0x0 [0])
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_device_tpm_read_hw_reg has 1 failures.

    • 0.spi_device_tpm_read_hw_reg.81035828603793043371962135529618223023094735383505209264276268256369262525004
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:39 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Job timed out after * minutes has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 0.spi_device_flash_mode_ignore_cmds.89435479951978538373020298394121798505430802201517292103154172260727124257982
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job timed out after 60 minutes