SRAM_CTRL/MAIN Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.350s	1.547ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.650s	43.561us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.640s	31.082us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.610s	172.847us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.630s	10.964us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	1.226ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.640s	31.082us	1	1	100.00
		sram_ctrl_csr_aliasing	0.630s	10.964us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.617m	55.353ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.636m	5.022ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.360m	19.263ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.455m	90.072ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.294s		0	1	0.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.422m	23.420ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.300s	6.589ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.691m	8.132ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.350s	2.335ms	1	1	100.00
		sram_ctrl_partial_access_b2b	26.195s		0	1	0.00
V2	max_throughput	sram_ctrl_max_throughput	4.220s	2.691ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.630s	2.890ms	1	1	100.00
		sram_ctrl_throughput_w_readback	23.570s	1.770ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.048m	19.134ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	19.732s		0	1	0.00
V2	stress_all	sram_ctrl_stress_all	1.274h	2.713s	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.610s	12.672us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.470s	114.956us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.470s	114.956us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.650s	43.561us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	31.082us	1	1	100.00
		sram_ctrl_csr_aliasing	0.630s	10.964us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	20.860us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.650s	43.561us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	31.082us	1	1	100.00
		sram_ctrl_csr_aliasing	0.630s	10.964us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	20.860us	1	1	100.00
V2		TOTAL			14	17	82.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	28.050s	7.067ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
		sram_ctrl_tl_intg_err	1.110s	102.162us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.110s	102.162us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.048m	19.134ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.048m	19.134ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.640s	31.082us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.691m	8.132ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.691m	8.132ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.691m	8.132ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.300s	6.589ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.550s	675.533us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	28.050s	7.067ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.750s	1.379ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.350s	1.547ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.350s	1.547ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.691m	8.132ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.300s	6.589ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.350s	1.547ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.600s	8.618us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	27.650s	5.268ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 0.sram_ctrl_bijection.43713501153951254842271458249494716964510534586266762806197953624353571635276
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:33 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_partial_access_b2b has 1 failures.

    • 0.sram_ctrl_partial_access_b2b.2153043150559023702029009939247662026656641258536697246203678629264127613472
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:33 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_ram_cfg has 1 failures.

    • 0.sram_ctrl_ram_cfg.19058722264801229219515552424302417939445652962996859132955799529672439625549
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:33 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.95941584833396855169975093560934970665136382812123525862271961457628247592964
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   8617607 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8617607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---