SRAM_CTRL/RET Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.760s	273.294us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	13.207us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.620s	31.321us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.140s	966.527us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	114.988us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.270s	39.059us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.620s	31.321us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	114.988us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.370s	1.338ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.060s	76.300us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.309m	18.379ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.583m	2.386ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	37.370s	1.641ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.166m	10.046ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.190s	191.294us	1	1	100.00
V2	executable	sram_ctrl_executable	3.640m	7.036ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	28.710s	2.283ms	1	1	100.00
		sram_ctrl_partial_access_b2b	26.049s		0	1	0.00
V2	max_throughput	sram_ctrl_max_throughput	28.240s	122.790us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.620s	630.714us	1	1	100.00
		sram_ctrl_throughput_w_readback	40.060s	1.389ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.140m	10.372ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.710s	74.770us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	9.523m	31.582ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	15.984s		0	1	0.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.190s	89.717us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.190s	89.717us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	13.207us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	31.321us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	114.988us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	19.896us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	13.207us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	31.321us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	114.988us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	19.896us	1	1	100.00
V2		TOTAL			15	17	88.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.400s	876.421us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
		sram_ctrl_tl_intg_err	1.210s	896.105us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.210s	896.105us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.140m	10.372ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.140m	10.372ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.620s	31.321us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.640m	7.036ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.640m	7.036ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.640m	7.036ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.190s	191.294us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.790s	36.676us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.400s	876.421us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.700s	23.486us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.760s	273.294us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.760s	273.294us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.640m	7.036ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.190s	191.294us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.760s	273.294us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.600s	10.136us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.890m	1.168ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test sram_ctrl_partial_access_b2b has 1 failures.

    • 0.sram_ctrl_partial_access_b2b.60963863989845510324596019833974812852472849398635166984535306224677146596171
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:27 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_alert_test has 1 failures.

    • 0.sram_ctrl_alert_test.91147291687457845912231315953886677307322631482580297539797995312775159207187
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:28 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.94487140285859574177687397048868321409740214952286912329967561089958313131412
      Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23485502 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x16) != exp (0x72)
        UVM_INFO @  23485502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.89665962362017398987981385268278801900903741096595204183052606231952953608794
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10136276 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10136276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---