SYSRST_CTRL Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.570s	2.115ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.710s	2.494ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.920s	2.438ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.050s	2.546ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.450s	6.074ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.810s	2.121ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	14.360s	37.356ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	3.130s	5.052ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.570s	2.051ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.810s	2.121ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.130s	5.052ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.196m	120.611ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.443m	47.745ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	4.400s	3.418ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.480s	3.501ms	0	1	0.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	18.253s		0	1	0.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.270s	2.077ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	5.730s	3.489ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.660s	2.638ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	20.298s		0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	43.170s	30.382ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	20.920s	15.268ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.870s	2.015ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.190s	2.050ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.720s	2.079ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.720s	2.079ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.450s	6.074ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.810s	2.121ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.130s	5.052ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	3.550s	4.369ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.450s	6.074ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.810s	2.121ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.130s	5.052ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	3.550s	4.369ms	1	1	100.00
V2		TOTAL			12	15	80.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.225m	42.014ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	6.060s	22.402ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	6.060s	22.402ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	9.190s	4.523ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	27	88.89

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test sysrst_ctrl_pin_override_test has 1 failures.

    • 0.sysrst_ctrl_pin_override_test.104433975011260024761214257807365461030928458484013143394618132735790414136912
      Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:25 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.34750177431041717694835131226812348898221971419778526535212118065226552549671
      Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:25 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 0.sysrst_ctrl_edge_detect.114750151848341711848250403620935066426115247796795052214482568634262253860700
      Line 388, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 3501417860 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 3501438267 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 3501438267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---