UART Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke			0	1	0.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	55.852us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.580s	16.172us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	20.240s		0	1	0.00
V1	csr_aliasing	uart_csr_aliasing	0.690s	545.672us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.730s	31.168us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.580s	16.172us	1	1	100.00
		uart_csr_aliasing	0.690s	545.672us	1	1	100.00
V1		TOTAL			4	6	66.67
V2	base_random_seq	uart_tx_rx			0	1	0.00
V2	parity	uart_smoke			0	1	0.00
		uart_tx_rx			0	1	0.00
V2	parity_error	uart_intr			0	1	0.00
		uart_rx_parity_err			0	1	0.00
V2	watermark	uart_tx_rx			0	1	0.00
		uart_intr			0	1	0.00
V2	fifo_full	uart_fifo_full			0	1	0.00
V2	fifo_overflow	uart_fifo_overflow			0	1	0.00
V2	fifo_reset	uart_fifo_reset			0	1	0.00
V2	rx_frame_err	uart_intr			0	1	0.00
V2	rx_break_err	uart_intr			0	1	0.00
V2	rx_timeout	uart_intr			0	1	0.00
V2	perf	uart_perf			0	1	0.00
V2	sys_loopback	uart_loopback			0	1	0.00
V2	line_loopback	uart_loopback			0	1	0.00
V2	rx_noise_filter	uart_noise_filter			0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter			0	1	0.00
V2	tx_overide	uart_tx_ovrd			0	1	0.00
V2	rx_oversample	uart_rx_oversample			0	1	0.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly			0	1	0.00
V2	stress_all	uart_stress_all			0	1	0.00
V2	alert_test	uart_alert_test			0	1	0.00
V2	intr_test	uart_intr_test	0.590s	22.416us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.900s	84.055us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.900s	84.055us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	55.852us	1	1	100.00
		uart_csr_rw	0.580s	16.172us	1	1	100.00
		uart_csr_aliasing	0.690s	545.672us	1	1	100.00
		uart_same_csr_outstanding	0.660s	20.417us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	55.852us	1	1	100.00
		uart_csr_rw	0.580s	16.172us	1	1	100.00
		uart_csr_aliasing	0.690s	545.672us	1	1	100.00
		uart_same_csr_outstanding	0.660s	20.417us	1	1	100.00
V2		TOTAL			3	18	16.67
V2S	tl_intg_err	uart_sec_cm			0	1	0.00
		uart_tl_intg_err	0.860s	55.029us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.860s	55.029us	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset			0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			8	27	29.63

Failure Buckets

• Job killed most likely because its dependent job failed. has 18 failures:

  • Test uart_smoke has 1 failures.

    • 0.uart_smoke.42698175152534831840127638793514359254358324297960205537630243191263644253424
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_smoke/latest/run.log

  • Test uart_tx_rx has 1 failures.

    • 0.uart_tx_rx.80956012055375431657144816261741098278388438130662599743620614620311652638891
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tx_rx/latest/run.log

  • Test uart_fifo_full has 1 failures.

    • 0.uart_fifo_full.66801361283674754476560467805453541556451075340941737872774955646295048956367
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log

  • Test uart_fifo_overflow has 1 failures.

    • 0.uart_fifo_overflow.68301542882425563013952701420901533608577089490758606161339445752360581508899
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_overflow/latest/run.log

  • Test uart_fifo_reset has 1 failures.

    • 0.uart_fifo_reset.14162243335419945098585335696847725203916492689142996339158405619648387926506
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_reset/latest/run.log

  • ... and 13 more tests.

• Job returned non-zero exit code has 2 failures:

  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/uart-sim-vcs/default/build.log

        recompiling module tb
        All of 75 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 14.339 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

  • Test uart_csr_bit_bash has 1 failures.

    • 0.uart_csr_bit_bash.74390104742990764240977302347726264492625741350433377391802169795361953161540
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_bit_bash/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 16 20:32 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255