CHIP Simulation Results

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: `f6ac363`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	17.686s		0	1	0.00
		chip_sw_example_rom	17.695s		0	1	0.00
		chip_sw_example_manufacturer	15.012s		0	1	0.00
		chip_sw_example_concurrency	13.569s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	1	0.00
V1	csr_rw	chip_csr_rw			0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	1	0.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
		chip_csr_rw			0	1	0.00
V1	xbar_smoke	xbar_smoke	6.100s	209.469us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	17.786s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	17.786s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	17.786s		0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	34.093s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	34.093s		0	1	0.00
		chip_sw_uart_tx_rx_idx1	34.569s		0	1	0.00
		chip_sw_uart_tx_rx_idx2	33.029s		0	1	0.00
		chip_sw_uart_tx_rx_idx3	33.124s		0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.534s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	19.484s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.428s		0	1	0.00
V1		TOTAL			1	18	5.56
V2	chip_pin_mux	chip_padctrl_attributes	29.279s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	29.279s		0	1	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	10.576s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.151s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	9.551s		0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	19.570s		0	1	0.00
		chip_tap_straps_testunlock0	19.885s		0	1	0.00
		chip_tap_straps_rma	16.987s		0	1	0.00
		chip_tap_straps_prod	18.567s		0	1	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	32.672s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.404s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	11.359s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	11.359s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.932s		0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	35.535m	25.134ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.320s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	16.463s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.717s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.342s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	16.353s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	16.405s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	16.768s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	21.304s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.262s		0	1	0.00
		chip_sw_clkmgr_jitter	16.739s		0	1	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	16.566s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	20.846s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	20.206s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	18.916s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	20.206s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.230m	2.122ms	1	1	100.00
		chip_sw_aes_smoketest	1.992m	2.951ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.582m	3.138ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.930m	3.026ms	1	1	100.00
		chip_sw_csrng_smoketest	47.729s		0	1	0.00
		chip_sw_entropy_src_smoketest	49.977s		0	1	0.00
		chip_sw_gpio_smoketest	2.219m	2.297ms	1	1	100.00
		chip_sw_hmac_smoketest	27.060s		0	1	0.00
		chip_sw_kmac_smoketest	2.656m	3.439ms	1	1	100.00
		chip_sw_otbn_smoketest	18.426m	11.368ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.414m	6.442ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.260m	6.316ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.326m	3.529ms	1	1	100.00
		chip_sw_rv_timer_smoketest	37.127s		0	1	0.00
		chip_sw_rstmgr_smoketest	1.804m	2.979ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.002m	2.598ms	1	1	100.00
		chip_sw_uart_smoketest	2.289m	3.200ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.207m	2.501ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.622m	4.356ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	34.608s		0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	33.469m	14.847ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.417m	14.255ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.499m	3.204ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.146m	3.183ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	10.001s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	11.728s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	xbar_base_random_sequence	xbar_random	38.067s		0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.310s	47.130us	1	1	100.00
		xbar_smoke_large_delays	36.800s	6.489ms	1	1	100.00
		xbar_smoke_slow_rsp	43.920s	5.285ms	1	1	100.00
		xbar_random_zero_delays	14.910s	269.565us	1	1	100.00
		xbar_random_large_delays	25.928s		0	1	0.00
		xbar_random_slow_rsp	31.720s		0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	26.210s	1.106ms	1	1	100.00
		xbar_error_and_unmapped_addr	11.530s	496.280us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	43.960s	2.215ms	1	1	100.00
		xbar_error_and_unmapped_addr	11.530s	496.280us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	45.850s	976.877us	1	1	100.00
		xbar_access_same_device_slow_rsp	3.832m	30.316ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	34.820s	2.180ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.414m	3.617ms	1	1	100.00
		xbar_stress_all_with_error	2.173m	6.729ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.252m	4.799ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.084m	382.166us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	33.469m	14.847ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	30.220m	24.901ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	33.750m	14.702ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	3.421m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2.420m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2.896m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3.241m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	33.505m	14.670ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2.532m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	3.711m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.668s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.410s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	3.796m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	2.592m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	3.133m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	2.154m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	3.284m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.420s	10.180us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	2.371m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.300s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	19.358s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.499m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	23.483s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	1.387m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	5.730m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.050s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	35.041s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.165s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.200s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	43.063s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.890s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.840s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.922m	11.588ms	1	1	100.00
		rom_e2e_asm_init_dev	17.235s		0	1	0.00
		rom_e2e_asm_init_prod	36.404m	17.026ms	1	1	100.00
		rom_e2e_asm_init_prod_end	35.636m	16.067ms	1	1	100.00
		rom_e2e_asm_init_rma	19.471s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	33.950m	15.493ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	32.628m	15.136ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	33.939m	14.985ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.798m	16.176ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.247s		0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.247s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	16.412s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.342s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	13.697s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	16.033s		0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.870s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.664s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	15.132s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	18.222s		0	1	0.00
		chip_plic_all_irqs_10	18.819s		0	1	0.00
		chip_plic_all_irqs_20	19.733s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.239s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.059s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.237s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.182s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.763s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.178s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.291s		0	1	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.448s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.707s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	16.624s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.414m	6.442ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	16.624s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.884s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.884s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	16.359s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.205s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	15.727s		0	1	0.00
		chip_sw_aes_idle	16.033s		0	1	0.00
		chip_sw_hmac_enc_idle	17.303s		0	1	0.00
		chip_sw_kmac_idle	20.825s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	20.111s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	15.717s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	17.703s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	19.708s		0	1	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	18.337s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.285s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	17.857s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.434s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.800s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.481s		0	1	0.00
		chip_sw_ast_clk_outputs	16.932s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.388s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.434s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.540s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.320s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	16.463s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.717s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.342s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	16.353s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	16.405s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	16.768s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	21.304s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.262s		0	1	0.00
		chip_sw_clkmgr_jitter	16.739s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	18.410s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	17.244s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	15.984s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.303s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	16.303s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	15.726s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.091s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	15.301s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	17.358s		0	1	0.00
		chip_sw_flash_init_reduced_freq	9.971s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	21.490s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.932s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	17.950s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	19.055s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.178s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.202s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	17.253s		0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	18.993s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	19.629s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.207s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	16.934s		0	1	0.00
		chip_sw_edn_entropy_reqs	17.309s		0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	16.934s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.202s		0	1	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	13.746s		0	1	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.538s		0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.097s		0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en	16.463s		0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	18.792s		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en	18.320s		0	1	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	14.954s		0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.538s		0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	15.922s		0	1	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	14.954s		0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	15.069s		0	1	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	15.937s		0	1	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	15.937s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	16.934s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	16.405s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	17.303s		0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	16.403s		0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	16.774s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.116s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	17.424s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	18.748s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	18.959s		0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	16.768s		0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	17.087s		0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.870s		0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	10.296s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	20.178s		0	1	0.00
		chip_sw_kmac_mode_kmac	22.643s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	21.304s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	20.773s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.858s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	20.825s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	15.132s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	19.570s		0	1	0.00
		chip_tap_straps_rma	16.987s		0	1	0.00
		chip_tap_straps_prod	18.567s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	15.908s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.820s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	17.049s		0	1	0.00
		chip_sw_flash_rma_unlocked	14.954s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.275s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.802s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.484s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.797s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
		chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	19.756s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	20.778s		0	1	0.00
		chip_prim_tl_access			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.388s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.285s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	17.857s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.434s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.800s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.481s		0	1	0.00
		chip_tap_straps_dev	19.570s		0	1	0.00
		chip_tap_straps_rma	16.987s		0	1	0.00
		chip_tap_straps_prod	18.567s		0	1	0.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	12.322s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	13.797s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	13.161s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	11.742s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.589s		0	1	0.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	9.814s		0	1	0.00
		chip_sw_lc_walkthrough_prod	17.236s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	19.641s		0	1	0.00
		chip_sw_lc_walkthrough_rma	19.379s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.589s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	20.171s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	18.376s		0	1	0.00
		rom_volatile_raw_unlock	54.610s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.991s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.717s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	15.727s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	15.727s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	15.727s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	15.238s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.538s		0	1	0.00
		chip_sw_otbn_mem_scramble	15.238s		0	1	0.00
		chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	22.224s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	18.306s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.538s		0	1	0.00
		chip_sw_otbn_mem_scramble	15.238s		0	1	0.00
		chip_sw_keymgr_key_derivation	16.772s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	22.224s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	18.306s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.305s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	15.908s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.275s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.802s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.484s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.797s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.110s		0	1	0.00
		chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.168s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	18.591s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.343s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	16.348s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	15.740s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	15.009s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.292s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	17.169s		0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	14.884s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	16.378s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.830s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	18.591s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.849s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.171s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.545s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.622s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	16.902s		0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.958s		0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	18.961s		0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.726s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	17.997s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	19.756s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	19.756s		0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	18.961s		0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	16.902s		0	1	0.00
		chip_sw_pwrmgr_wdog_reset	14.830s		0	1	0.00
		chip_sw_pwrmgr_smoketest	4.414m	6.442ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	14.864s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.225s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	18.327s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.059s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	17.059s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.291s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	16.831s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	15.452s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	16.831s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	18.306s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.225s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.225s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.956m	11.714ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.573m	13.757ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	14.864s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	17.250s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	19.675s		0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	16.987s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	18.222s		0	1	0.00
		chip_plic_all_irqs_10	18.819s		0	1	0.00
		chip_plic_all_irqs_20	19.733s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	18.980s		0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	17.052s		0	1	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	33.469m	14.847ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	18.060s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	16.896s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	17.430s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.006s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	22.224s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.262s		0	1	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	19.655s		0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble	19.337s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	20.778s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	12.267s		0	1	0.00
		chip_sw_data_integrity_escalation	11.359s		0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.958s		0	1	0.00
		chip_sw_sysrst_ctrl_reset	16.363s		0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	17.051s		0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	16.312s		0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	16.462s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.363s		0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.363s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	17.645s		0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	17.645s		0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	16.890s		0	1	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	14.247s		0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	33.640s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	33.311s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	34.054s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	33.118s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	32.932s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	28.693s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	34.327s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	15.820s		0	1	0.00
V2		TOTAL			42	275	15.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	16.461s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	18.941s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_sw_coremark	chip_sw_coremark	20.746s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	4.849m	3.411ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.357m	12.217ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.026m	4.643ms	0	1	0.00
		rom_e2e_jtag_debug_rma	14.899m	11.597ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.531m	4.415ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.717m	4.171ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.675m	4.897ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.455s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	16.316s		0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	17.462s		0	1	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.597s		0	1	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	18.261s		0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	19.732s		0	1	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	6.886m	5.116ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.852s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.436s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	15.186s		0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	16.942s		0	1	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	18.961s		0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.357m	12.217ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.026m	4.643ms	0	1	0.00
		rom_e2e_jtag_debug_rma	14.899m	11.597ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	17.097s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	12.267s		0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	18.260s		0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	18.260s		0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	18.696s		0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	34.093s		0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	22.583s		0	1	0.00
V3		TOTAL			6	23	26.09
	Unmapped tests	chip_sival_flash_info_access	12.628s		0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.144s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	14.903s		0	1	0.00
		chip_sw_otp_ctrl_descrambling	13.902s		0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel	17.716s		0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	16.402s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	17.455s		0	1	0.00
		TOTAL			49	325	15.08

Failure Buckets

Job returned non-zero exit code has 253 failures:

Test chip_sw_example_flash has 1 failures.

0.chip_sw_example_flash.78831367101138778638884476662351697509656526849785212880679710801223858738410
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_flash_sim_dv".
  Building "//sw/device/tests:example_test_from_flash_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_flash_sim_dv
  Computing main repo mapping:
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.75898740497329304965522106676234974781522663844875039824555214692139220626570
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
  Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
  Another command (pid=910529) is running. Waiting for it to complete on the server (server_pid=905959)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.67824289694541948313082158922977251532741721463223422672074601093649705610910
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "@manufacturer_test_hooks//:example_test_sim_dv".
  Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true @manufacturer_test_hooks//:example_test_sim_dv
  Another command (pid=910529) is running. Waiting for it to complete on the server (server_pid=905959)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.89318069959240884826337348198026103462584860458820143232686686861077674607021
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_concurrency_test_sim_dv".
  Building "//sw/device/tests:example_concurrency_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_concurrency_test_sim_dv
  Another command (pid=910529) is running. Waiting for it to complete on the server (server_pid=905959)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sival_flash_info_access has 1 failures.

0.chip_sival_flash_info_access.70136559911999204164213351473257237633983761679859442592117266681967713367298
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:flash_ctrl_info_access_lc_sim_dv".
  Building "//sw/device/tests:flash_ctrl_info_access_lc_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:flash_ctrl_info_access_lc_sim_dv
  Another command (pid=910529) is running. Waiting for it to complete on the server (server_pid=905959)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

... and 248 more tests.

Job killed most likely because its dependent job failed. has 9 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.105528562684755286582673234648010796359468681620876476601583418104879642527072
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.59979620449668916430629943280831638286191771463980936102503698486554305923748
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.48212079986440767597344435434920027210308393720128031956072580597661247980639
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.13945550195556668645038646213770965959510354342705665423459909496769925280410
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
- Test chip_prim_tl_access has 1 failures.
  - 0.chip_prim_tl_access.67611619566432690041101853745915563819283792098551231922392371038107892579601
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
- ... and 4 more tests.
Job timed out after * minutes has 2 failures:
- Test cover_reg_top has 1 failures.
  - cover_reg_top
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cover_reg_top/build.log
```
  Job timed out after 60 minutes
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.112150612588176391505440885439303959584957016193471041084126413112338560658703
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.111391716524825591669921866380857112054294647662125866522295528210444530303558
    Line 831, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.61586098028151301475415431240702475335136888265383551357076988241170002772493
    Line 679, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.57925205984404522674414908796817062127748156089669500555754226162808207731138
    Line 678, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.14038010867522175488286047249487514229869729360551263251901809621086894779158
    Line 647, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.31385864357899094934919341698416974055954448481752038147428494419210897094439
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3203.651000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3203.651000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.39641554943967053175108208293787471613780659634664598955042726131332483922817
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3182.730000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3182.730000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.21458523386249328146422881977786129349953052910738477738986132573462158747798
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 25133.603660 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 25133.603660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.103388170456930019353141686229647615216967398021858806315659488398688522098082
    Line 627, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3411.243316 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3411.243316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.80730609741277857167400006205092340698867835161823245968598500924716674675067
    Line 696, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.29839510428426700591267195050234576306783652833400534644424377621938017344095
    Line 722, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.85530528224283213021561818648189497328650517202693729575882354011577164315683
    Line 650, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.16068648703863054106520834760869968979637873464328969128561297136057772803592
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 4642.786686 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4642.786686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.102430095360702647704336296465072916874503486141963019082929500293450902712104
    Line 447, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 14255.379441 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 14255.379441 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```