30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 1.080s | 1.081ms | 1 | 1 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 1.190s | 336.246us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 40.780s | 20.197ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 2.310s | 1.191ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 0.990s | 653.545us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 1.190s | 336.246us | 1 | 1 | 100.00 |
| adc_ctrl_csr_aliasing | 2.310s | 1.191ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 0 | 1 | 0.00 | ||
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 0 | 1 | 0.00 | ||
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 0 | 1 | 0.00 | ||
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 0 | 1 | 0.00 | ||
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 0 | 1 | 0.00 | ||
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 0 | 1 | 0.00 | ||
| V2 | filters_both | adc_ctrl_filters_both | 0 | 1 | 0.00 | ||
| V2 | clock_gating | adc_ctrl_clock_gating | 0 | 1 | 0.00 | ||
| V2 | poweron_counter | adc_ctrl_poweron_counter | 0 | 1 | 0.00 | ||
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 0 | 1 | 0.00 | ||
| V2 | fsm_reset | adc_ctrl_fsm_reset | 0 | 1 | 0.00 | ||
| V2 | stress_all | adc_ctrl_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | adc_ctrl_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | adc_ctrl_intr_test | 1.420s | 531.737us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 1.430s | 628.495us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 1.430s | 628.495us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 1.080s | 1.081ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 1.190s | 336.246us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 2.310s | 1.191ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 26.086s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 1.080s | 1.081ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 1.190s | 336.246us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 2.310s | 1.191ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 26.086s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 2 | 16 | 12.50 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| adc_ctrl_tl_intg_err | 5.400s | 8.946ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 5.400s | 8.946ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 8 | 25 | 32.00 |
Job killed most likely because its dependent job failed. has 16 failures:
Test adc_ctrl_smoke has 1 failures.
Test adc_ctrl_filters_polled has 1 failures.
Test adc_ctrl_filters_polled_fixed has 1 failures.
Test adc_ctrl_filters_interrupt has 1 failures.
Test adc_ctrl_filters_interrupt_fixed has 1 failures.
... and 11 more tests.
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/default/build.log
Job timed out after 60 minutes
Job returned non-zero exit code has 1 failures:
0.adc_ctrl_same_csr_outstanding.93065233460052961395386271663209549930434348131365742444496773903134131167980
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest/run.log
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255