30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 22.697s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.750s | 15.771us | 1 | 1 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 0.760s | 32.954us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 2.510s | 142.866us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.170s | 128.654us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0.860s | 33.262us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.760s | 32.954us | 1 | 1 | 100.00 |
| edn_csr_aliasing | 1.170s | 128.654us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | firmware | edn_genbits | 0.950s | 57.869us | 1 | 1 | 100.00 |
| V2 | csrng_commands | edn_genbits | 0.950s | 57.869us | 1 | 1 | 100.00 |
| V2 | genbits | edn_genbits | 0.950s | 57.869us | 1 | 1 | 100.00 |
| V2 | interrupts | edn_intr | 0.950s | 22.389us | 1 | 1 | 100.00 |
| V2 | alerts | edn_alert | 0.870s | 75.777us | 1 | 1 | 100.00 |
| V2 | errs | edn_err | 0.960s | 28.149us | 1 | 1 | 100.00 |
| V2 | disable | edn_disable | 22.680s | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 26.974s | 0 | 1 | 0.00 | |||
| V2 | stress_all | edn_stress_all | 2.460s | 654.661us | 1 | 1 | 100.00 |
| V2 | intr_test | edn_intr_test | 0.700s | 46.806us | 1 | 1 | 100.00 |
| V2 | alert_test | edn_alert_test | 0.810s | 153.466us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 1.290s | 54.925us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 1.290s | 54.925us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.750s | 15.771us | 1 | 1 | 100.00 |
| edn_csr_rw | 0.760s | 32.954us | 1 | 1 | 100.00 | ||
| edn_csr_aliasing | 1.170s | 128.654us | 1 | 1 | 100.00 | ||
| edn_same_csr_outstanding | 1.130s | 74.479us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.750s | 15.771us | 1 | 1 | 100.00 |
| edn_csr_rw | 0.760s | 32.954us | 1 | 1 | 100.00 | ||
| edn_csr_aliasing | 1.170s | 128.654us | 1 | 1 | 100.00 | ||
| edn_same_csr_outstanding | 1.130s | 74.479us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 11 | 81.82 | |||
| V2S | tl_intg_err | edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 |
| edn_tl_intg_err | 1.320s | 190.381us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 0.810s | 31.389us | 1 | 1 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 0.870s | 75.777us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0.870s | 75.777us | 1 | 1 | 100.00 |
| edn_sec_cm | 3.110s | 946.951us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0.870s | 75.777us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 1.320s | 190.381us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 17 | 21 | 80.95 |
Job returned non-zero exit code has 3 failures:
Test edn_smoke has 1 failures.
0.edn_smoke.36524494510975847245787165820517011797797955467505603397594975523429798755155
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:06 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test edn_disable has 1 failures.
0.edn_disable.70426830449687756552436442748060016370218901383642436543610766241018043305778
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_disable/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:06 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test edn_disable_auto_req_mode has 1 failures.
0.edn_disable_auto_req_mode.92407391190444178207166093910765591158488640837690947363694178389000077904154
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:06 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 1 failures:
0.edn_stress_all_with_rand_reset.23703186836178334023802279668015342269391382292383055351157548262146623195992
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes