30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 16.910s | 5.325ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 20.237s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 57.365us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.700s | 24.230us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.570s | 619.048us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.000s | 261.865us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.820s | 38.247us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.700s | 24.230us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.000s | 261.865us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 7 | 85.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.400s | 1.576ms | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 3.316m | 4.610ms | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 3.369m | 93.759ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.620s | 75.420us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 3.342m | 6.424ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 35.260s | 10.162ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 21.939s | 0 | 1 | 0.00 | |
| i2c_host_fifo_fmt_empty | 5.930s | 1.356ms | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 3.530s | 206.646us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 28.750s | 8.146ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 9.060s | 931.339us | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.410s | 100.655us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 1.770s | 496.015us | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 28.900s | 103.024ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 3.400s | 804.509us | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 18.402s | 0 | 1 | 0.00 | |
| i2c_target_intr_smoke | 3.750s | 1.056ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.910s | 289.756us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 26.467s | 0 | 1 | 0.00 | |||
| V2 | target_fifo_full | i2c_target_stress_wr | 1.096m | 51.034ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 18.402s | 0 | 1 | 0.00 | |||
| i2c_target_intr_stress_wr | 1.491m | 15.957ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 3.800s | 2.328ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 7.480s | 3.853ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 3.820s | 4.058ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.130s | 1.169ms | 1 | 1 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.780s | 515.895us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.920s | 1.420ms | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 3.369m | 93.759ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 1.320s | 299.654us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 9.060s | 931.339us | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 0.710s | 11.195us | 0 | 1 | 0.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.980s | 2.126ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.790s | 1.190ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.020s | 287.435us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 4.810s | 596.558us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.260s | 354.209us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 15.883s | 0 | 1 | 0.00 | |
| V2 | intr_test | i2c_intr_test | 0.620s | 51.191us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.400s | 80.218us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.400s | 80.218us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 57.365us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.700s | 24.230us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.000s | 261.865us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 200.816us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 57.365us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.700s | 24.230us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.000s | 261.865us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 200.816us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 29 | 38 | 76.32 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.090s | 306.801us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.780s | 79.916us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.090s | 306.801us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 23.120s | 4.275ms | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.070s | 448.490us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.470s | 1.727ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 37 | 50 | 74.00 |
Job returned non-zero exit code has 5 failures:
Test i2c_host_fifo_reset_fmt has 1 failures.
0.i2c_host_fifo_reset_fmt.28048587561125860229689837694495278458931201240762556594261877925399132591588
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_smoke has 1 failures.
0.i2c_target_smoke.21512189717616883519458611511176251242406564683461248191316689211534860768526
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_stress_rd has 1 failures.
0.i2c_target_stress_rd.5428687372125930828426825676795459748521663796155410100184030112414632839720
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_rd/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_fifo_reset_tx has 1 failures.
0.i2c_target_fifo_reset_tx.39395776073046372779143818339328152812336455416411747070311998144101428959740
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_alert_test has 1 failures.
0.i2c_alert_test.62253855302574932150751215810294917309025479758802214882476043095994178244199
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:17 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:
Test i2c_host_error_intr has 1 failures.
0.i2c_host_error_intr.113176124266817399724312261121932032899823264390992342119113211936791942721187
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 1576364262 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1576364262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.95555865140786902657635613808579628547850730572939072849058837432655640216986
Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1726997878 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1726997878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
0.i2c_host_stress_all.38163037773662580859403211526200823194939978335237219352252895832278662399700
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 4609934681 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2492375
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.111709279305011036848300666120480299005967489482389672393260400383768549018168
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 496014964 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 496014964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.30268063778867417328972990868811178956623721747716749515276765441308259455278
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 448490334 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 448490334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.i2c_host_stress_all_with_rand_reset.49550577793786889904912315774185029943070527406404769821166731396857172008834
Line 141, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4275156809 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4275156809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
0.i2c_host_mode_toggle.99558152507635493686711005239457147517455199079504376027548298175128530462384
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 100654681 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
0.i2c_target_tx_stretch_ctrl.55655511178503799045909496595384374684853882258461450477529580117952405034481
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.