KEYMGR Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.499s		0	1	0.00
V1	random	keymgr_random	4.770s	534.359us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.120s	34.750us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.810s	88.133us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.180s	132.574us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	2.560s	137.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	0.970s	33.382us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.810s	88.133us	1	1	100.00
		keymgr_csr_aliasing	2.560s	137.935us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	2.280s	163.645us	1	1	100.00
V2	sideload	keymgr_sideload	2.920s	151.439us	1	1	100.00
		keymgr_sideload_kmac	1.740s	42.672us	1	1	100.00
		keymgr_sideload_aes	1.510s	417.137us	1	1	100.00
		keymgr_sideload_otbn	1.730s	65.407us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.180s	387.790us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.210s	106.711us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.590s	60.595us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.530s	4.950ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.670s	129.808us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.190s	89.494us	1	1	100.00
V2	stress_all	keymgr_stress_all			0	1	0.00
V2	intr_test	keymgr_intr_test	0.710s	35.403us	1	1	100.00
V2	alert_test	keymgr_alert_test	27.353s		0	1	0.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.170s	140.368us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.170s	140.368us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.120s	34.750us	1	1	100.00
		keymgr_csr_rw	0.810s	88.133us	1	1	100.00
		keymgr_csr_aliasing	2.560s	137.935us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	207.983us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.120s	34.750us	1	1	100.00
		keymgr_csr_rw	0.810s	88.133us	1	1	100.00
		keymgr_csr_aliasing	2.560s	137.935us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	207.983us	1	1	100.00
V2		TOTAL			14	16	87.50
V2S	sec_cm_additional_check	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
		keymgr_tl_intg_err	2.680s	200.891us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.570s	344.787us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.570s	344.787us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.570s	344.787us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.570s	344.787us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.330s	805.852us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.680s	200.891us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.570s	344.787us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.280s	163.645us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.770s	534.359us	1	1	100.00
		keymgr_csr_rw	0.810s	88.133us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.770s	534.359us	1	1	100.00
		keymgr_csr_rw	0.810s	88.133us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.770s	534.359us	1	1	100.00
		keymgr_csr_rw	0.810s	88.133us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.210s	106.711us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.670s	129.808us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.670s	129.808us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.770s	534.359us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	15.156s		0	1	0.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.510s	381.520us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.210s	106.711us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.510s	381.520us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.510s	381.520us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.510s	381.520us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.830s	421.521us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.510s	381.520us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.380s	468.526us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	30	83.33

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test keymgr_smoke has 1 failures.

    • 0.keymgr_smoke.76730339949073722883198322530039763761078375193522731324929049413724359011939
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_sideload_protect has 1 failures.

    • 0.keymgr_sideload_protect.65044623164735778048872636082142003935817895603322026180754929235727031803213
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_protect/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_alert_test has 1 failures.

    • 0.keymgr_alert_test.115097321602541210998738393096254633116670642928512812118139531456592010227308
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_alert_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Job timed out after * minutes has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.38993669781052692155447833620584944938950891546073720103355623903031615621113
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.20079610972371552929181255526461110191169363561081399605330698100052294993642
      Line 734, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 468526313 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 468526313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---