KMAC/MASKED Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	47.610s	4.073ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.940s	34.976us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.810s	35.362us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.180s	1.488ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.280s	202.811us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.160s	28.532us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.810s	35.362us	1	1	100.00
		kmac_csr_aliasing	3.280s	202.811us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.680s	13.068us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.940s	186.246us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	24.300s		0	1	0.00
V2	burst_write	kmac_burst_write	6.640m	25.155ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.217s		0	1	0.00
		kmac_test_vectors_sha3_256	27.670s	6.753ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.829m	132.406ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.741m	38.952ms	1	1	100.00
		kmac_test_vectors_shake_128	1.722m	14.848ms	1	1	100.00
		kmac_test_vectors_shake_256	1.428m	18.044ms	1	1	100.00
		kmac_test_vectors_kmac	1.660s	163.064us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.710s	70.402us	1	1	100.00
V2	sideload	kmac_sideload	38.750s	3.723ms	1	1	100.00
V2	app	kmac_app	2.023m	20.022ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.296m	7.310ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	59.290s	34.860ms	1	1	100.00
V2	error	kmac_error	3.508m	44.152ms	1	1	100.00
V2	key_error	kmac_key_error	2.230s	694.309us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.300s	246.975us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.750s	466.734us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	0.820s	18.140us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	7.760s	1.326ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	0.980s	40.734us	1	1	100.00
V2	stress_all	kmac_stress_all	18.642m	19.525ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.690s	27.348us	1	1	100.00
V2	alert_test	kmac_alert_test	15.922s		0	1	0.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.540s	1.030ms	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.540s	1.030ms	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.940s	34.976us	1	1	100.00
		kmac_csr_rw	0.810s	35.362us	1	1	100.00
		kmac_csr_aliasing	3.280s	202.811us	1	1	100.00
		kmac_same_csr_outstanding	1.160s	89.691us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.940s	34.976us	1	1	100.00
		kmac_csr_rw	0.810s	35.362us	1	1	100.00
		kmac_csr_aliasing	3.280s	202.811us	1	1	100.00
		kmac_same_csr_outstanding	1.160s	89.691us	1	1	100.00
V2		TOTAL			23	26	88.46
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.660s	107.609us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.660s	107.609us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.660s	107.609us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.660s	107.609us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.870s	82.248us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	31.220s	3.491ms	1	1	100.00
		kmac_tl_intg_err	1.640s	570.069us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.640s	570.069us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	0.980s	40.734us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	47.610s	4.073ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	38.750s	3.723ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.660s	107.609us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	31.220s	3.491ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	31.220s	3.491ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	31.220s	3.491ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	47.610s	4.073ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	0.980s	40.734us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	31.220s	3.491ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	15.960s		0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	47.610s	4.073ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.225m	31.755ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			36	40	90.00

Failure Buckets

• Job returned non-zero exit code has 4 failures:

  • Test kmac_long_msg_and_output has 1 failures.

    • 0.kmac_long_msg_and_output.18819492927209709562833366777359730877235754160016582855485690519426103948020
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_test_vectors_sha3_224 has 1 failures.

    • 0.kmac_test_vectors_sha3_224.73607275277961926591997069016782161410701276293161509435678497487203802656961
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.15100645010718251818618387618351583157663710535270868877702033339908613064530
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mubi/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_alert_test has 1 failures.

    • 0.kmac_alert_test.58544486845544353035303703210375468141569874587984895638117842487591945346500
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_alert_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255