30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 21.840s | 674.419us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.770s | 142.239us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.770s | 80.357us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 14.050s | 5.986ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 4.840s | 543.304us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 1.950s | 793.853us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.770s | 80.357us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 4.840s | 543.304us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.680s | 46.099us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.180s | 279.618us | 1 | 1 | 100.00 |
| V1 | TOTAL | 8 | 8 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 5.899m | 64.385ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 5.368m | 34.464ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 26.070s | 7.059ms | 1 | 1 | 100.00 |
| kmac_test_vectors_sha3_256 | 30.150s | 13.946ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 12.662m | 40.017ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 18.224s | 0 | 1 | 0.00 | |||
| kmac_test_vectors_shake_128 | 1.877m | 14.292ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 22.861m | 300.762ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 1.680s | 178.601us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 16.121s | 0 | 1 | 0.00 | |||
| V2 | sideload | kmac_sideload | 1.937m | 18.405ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 2.225m | 9.371ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.054m | 35.295ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 37.510s | 31.859ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 2.306m | 2.798ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 5.820s | 5.518ms | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 28.846s | 0 | 1 | 0.00 | |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 8.930s | 432.919us | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 7.780s | 1.906ms | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 2.360s | 562.488us | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 0.980s | 68.445us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 5.300s | 890.636us | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.680s | 28.449us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.690s | 26.646us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 20.563s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | kmac_tl_errors | 20.563s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.770s | 142.239us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.770s | 80.357us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.840s | 543.304us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.070s | 23.918us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.770s | 142.239us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.770s | 80.357us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.840s | 543.304us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.070s | 23.918us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 22 | 26 | 84.62 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.360s | 206.135us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.360s | 206.135us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.360s | 206.135us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.360s | 206.135us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.020s | 125.267us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 32.830s | 13.016ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 13.935s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 13.935s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0.980s | 68.445us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 21.840s | 674.419us | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 1.937m | 18.405ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.360s | 206.135us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 32.830s | 13.016ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 32.830s | 13.016ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 32.830s | 13.016ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 21.840s | 674.419us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0.980s | 68.445us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 32.830s | 13.016ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 2.072m | 8.140ms | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 21.840s | 674.419us | 1 | 1 | 100.00 |
| V2S | TOTAL | 4 | 5 | 80.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 53.360s | 3.459ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 34 | 40 | 85.00 |
Job returned non-zero exit code has 5 failures:
Test kmac_sideload_invalid has 1 failures.
0.kmac_sideload_invalid.105874507003541262146021325041025808284938728706968903184541847997679584570676
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_test_vectors_sha3_512 has 1 failures.
0.kmac_test_vectors_sha3_512.25883519733519668183163026769581485455333941401462397522039304136568586686684
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_test_vectors_kmac_xof has 1 failures.
0.kmac_test_vectors_kmac_xof.10586818431940184131108831650903610358541994836233051290282265599079937407006
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_tl_errors has 1 failures.
0.kmac_tl_errors.61223129907487664422315237030629291205853953754798361422914573545409121540778
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_tl_intg_err has 1 failures.
0.kmac_tl_intg_err.104938709339599378452498092540514076946112974024024946080323424272783599541145
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.kmac_stress_all_with_rand_reset.10222892822896757639041984286694560457186379919819665634278092220089524282724
Line 288, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3458760925 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3458760925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---