30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 39.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 39.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | pattgen_csr_rw | 31.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 35.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 31.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 26.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 31.000s | 0 | 1 | 0.00 | |
| pattgen_csr_aliasing | 31.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 0 | 6 | 0.00 | |||
| V2 | perf | pattgen_perf | 27.000s | 0 | 1 | 0.00 | |
| V2 | cnt_rollover | cnt_rollover | 31.000s | 0 | 1 | 0.00 | |
| V2 | error | pattgen_error | 21.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | pattgen_stress_all | 26.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | pattgen_alert_test | 39.000s | 0 | 1 | 0.00 | |
| V2 | intr_test | pattgen_intr_test | 23.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 26.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 26.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 39.000s | 0 | 1 | 0.00 | |
| pattgen_csr_rw | 31.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 31.000s | 0 | 1 | 0.00 | |||
| pattgen_same_csr_outstanding | 26.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 39.000s | 0 | 1 | 0.00 | |
| pattgen_csr_rw | 31.000s | 0 | 1 | 0.00 | |||
| pattgen_csr_aliasing | 31.000s | 0 | 1 | 0.00 | |||
| pattgen_same_csr_outstanding | 26.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 0 | 8 | 0.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 21.000s | 0 | 1 | 0.00 | |
| pattgen_sec_cm | 28.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 21.000s | 0 | 1 | 0.00 | |
| V2S | TOTAL | 0 | 2 | 0.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 38.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 30.000s | 0 | 1 | 0.00 | ||
| TOTAL | 0 | 18 | 0.00 |
Job returned non-zero exit code has 18 failures:
Test pattgen_smoke has 1 failures.
0.pattgen_smoke.93573835456481500965233362894889634801355234762719034405319935445546932899546
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 17:08:11 UTC (total: 00:00:39)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_perf has 1 failures.
0.pattgen_perf.33743966632862353674378828318467413208958614256345727282832851465342982722304
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 17:07:59 UTC (total: 00:00:27)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_error has 1 failures.
0.pattgen_error.60007208720595387786647516384577281413150037734096830077040283188774356136614
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 17:07:53 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test cnt_rollover has 1 failures.
0.cnt_rollover.111103582510173078947701068123659658154113369109569536370269631243961239949980
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 17:08:04 UTC (total: 00:00:31)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test pattgen_inactive_level has 1 failures.
0.pattgen_inactive_level.93184023886225017142165163402959683066131107660719896978096893853711395397654
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 17:08:04 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 13 more tests.