PRIM_LFSR Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	Unmapped tests	prim_lfsr_fib_smoke	1.560s	1.455ms	1	1	100.00
		prim_lfsr_fib_test			0	1	0.00
		prim_lfsr_gal_test	2.919m	336.556ms	1	1	100.00
		prim_lfsr_gal_smoke	1.060s	1.270ms	1	1	100.00
		TOTAL			3	4	75.00

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test prim_lfsr_dw_24_fib has 1 failures.

    • prim_lfsr_dw_24_fib
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/build.log

        recompiling module prim_lfsr_tb
        All of 16 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 8.027 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test prim_lfsr_fib_test has 1 failures.
    • 0.prim_lfsr_fib_test.80165792892476760131510173507434360839796313822512250283956064182875294672428
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest/run.log