30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.260s | 963.352us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0 | 1 | 0.00 | ||
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 0 | 1 | 0.00 | ||
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0.980s | 539.421us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.040s | 273.962us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.670s | 139.048us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 14.444s | 0 | 1 | 0.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.160s | 585.022us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 16.144s | 0 | 1 | 0.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.750s | 365.146us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 22.409s | 0 | 1 | 0.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 0.980s | 539.421us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 28.623s | 0 | 1 | 0.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.220s | 387.473us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.670s | 139.048us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.710s | 112.147us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | rv_dm_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | rv_dm_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 0 | 1 | 0.00 | ||
| rv_dm_csr_rw | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | rv_dm_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 8 | 27 | 29.63 | |||
| V2 | idcode | rv_dm_smoke | 2.260s | 963.352us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.080s | 258.236us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.690s | 110.471us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.070s | 297.837us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.870s | 293.891us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 7.582m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 25.196s | 0 | 1 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 8.950m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 8.133m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.740s | 88.526us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 1.170s | 940.820us | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.800s | 123.724us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.760s | 129.939us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 19.470s | 10.734ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 0 | 1 | 0.00 | ||||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.650s | 90.706us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 1.570s | 2.233ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_dm_alert_test | 0.600s | 45.003us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 0 | 1 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 1 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 1 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 0 | 1 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 1 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 1 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 11 | 19 | 57.89 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.850s | 595.812us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 1.170s | 940.820us | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 20.648s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 1.170s | 940.820us | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 20.648s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 2.260s | 963.352us | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 0.890s | 97.927us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.930s | 156.558us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.930s | 156.558us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 0.890s | 97.927us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 5 | 60.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.670s | 42.656us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 0.620s | 15.190us | 1 | 1 | 100.00 | |
| TOTAL | 23 | 53 | 43.40 |
Job killed most likely because its dependent job failed. has 19 failures:
Test rv_dm_csr_aliasing has 1 failures.
Test rv_dm_jtag_dtm_csr_hw_reset has 1 failures.
Test rv_dm_jtag_dtm_csr_rw has 1 failures.
Test rv_dm_jtag_dtm_csr_bit_bash has 1 failures.
Test rv_dm_jtag_dtm_csr_aliasing has 1 failures.
... and 14 more tests.
Job returned non-zero exit code has 7 failures:
Test cover_reg_top has 1 failures.
cover_reg_top
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/cover_reg_top/build.log
recompiling module tb
All of 96 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 18.394 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.35698868145373678570257109941523313825356216816282828223121556610626737972602
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:04 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_dm_mem_tl_access_resuming has 1 failures.
0.rv_dm_mem_tl_access_resuming.59465288232311512698987627178084785385646679482103216324130535090591266474693
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:04 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_dm_cmderr_halt_resume has 1 failures.
0.rv_dm_cmderr_halt_resume.96945987603135833639063867451349732813464904209590052525375462596083080786256
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:04 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_dm_halt_resume_whereto has 1 failures.
0.rv_dm_halt_resume_whereto.76995514686650061515713355424471485896875563653829792822470564882952868819221
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:04 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.44498233956437529518626119574445278976235580438934224759711802719377380642809
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.65256452742845383493649546771094829909596881988120257238022123711570962822737
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.10802114794674283958081186715371438477949123413015102387943533275046705069196
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.50807321296054192566850592708523963949643023293645695095544927234414138576052
Line 89, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 290
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5750) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.72858641011450446467096658253890712243176734250982383544208801717959106172274
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 42655778 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5750) { a_addr: 'hecaaf468 a_data: 'h6421a63c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h46 a_opcode: 'h4 a_user: 'h194b9 d_param: 'h0 d_source: 'h46 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 42655778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---