30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.560s | 11.210us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 16.737us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.520s | 44.338us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.870s | 555.334us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.590s | 15.180us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.050s | 98.403us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.520s | 44.338us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.590s | 15.180us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.590s | 211.726us | 1 | 1 | 100.00 |
| V2 | disabled | rv_timer_disabled | 2.370s | 2.374ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 33.492s | 0 | 1 | 0.00 | |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 33.492s | 0 | 1 | 0.00 | |
| V2 | stress | rv_timer_stress_all | 1.500s | 927.440us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.540s | 13.165us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.560s | 18.699us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.080s | 91.759us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.080s | 91.759us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 16.737us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.520s | 44.338us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.590s | 15.180us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.680s | 31.069us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 16.737us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.520s | 44.338us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.590s | 15.180us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.680s | 31.069us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.740s | 257.415us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.700s | 183.183us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.700s | 183.183us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.550s | 50.453us | 1 | 1 | 100.00 |
| V3 | max_value | rv_timer_max | 0.550s | 39.868us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 6.350s | 4.654ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 3 | 3 | 100.00 | |||
| TOTAL | 18 | 19 | 94.74 |
Job returned non-zero exit code has 1 failures:
0.rv_timer_cfg_update_on_fly.26451411042969322216370258026058690658106378459413677091045715281098769628810
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255