SPI_DEVICE/1R1W Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm			0	1	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.950s	38.865us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.970s	112.135us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	13.650s	1.408ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.970s	4.300ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.200s	80.952us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.970s	112.135us	1	1	100.00
		spi_device_csr_aliasing	9.970s	4.300ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	12.564us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.330s	213.759us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	csb_read	spi_device_csb_read			0	1	0.00
V2	mem_parity	spi_device_mem_parity			0	1	0.00
V2	mem_cfg	spi_device_ram_cfg			0	1	0.00
V2	tpm_read	spi_device_tpm_rw			0	1	0.00
V2	tpm_write	spi_device_tpm_rw			0	1	0.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg			0	1	0.00
		spi_device_tpm_sts_read			0	1	0.00
V2	tpm_fully_random_case	spi_device_tpm_all			0	1	0.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	cmd_info_slots	spi_device_flash_all			0	1	0.00
V2	cmd_read_status	spi_device_intercept			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	cmd_read_jedec	spi_device_intercept			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	cmd_read_sfdp	spi_device_intercept			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	cmd_fast_read	spi_device_intercept			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	cmd_read_pipeline	spi_device_intercept			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	flash_cmd_upload	spi_device_upload			0	1	0.00
V2	mailbox_command	spi_device_mailbox			0	1	0.00
V2	mailbox_cross_outside_command	spi_device_mailbox			0	1	0.00
V2	mailbox_cross_inside_command	spi_device_mailbox			0	1	0.00
V2	cmd_read_buffer	spi_device_flash_mode			0	1	0.00
		spi_device_read_buffer_direct			0	1	0.00
V2	cmd_dummy_cycle	spi_device_mailbox			0	1	0.00
		spi_device_flash_all			0	1	0.00
V2	quad_spi	spi_device_flash_all			0	1	0.00
V2	dual_spi	spi_device_flash_all			0	1	0.00
V2	4b_3b_feature	spi_device_cfg_cmd			0	1	0.00
V2	write_enable_disable	spi_device_cfg_cmd			0	1	0.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm			0	1	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle			0	1	0.00
V2	stress_all	spi_device_stress_all			0	1	0.00
V2	alert_test	spi_device_alert_test			0	1	0.00
V2	intr_test	spi_device_intr_test	0.630s	13.951us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.600s	257.489us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.600s	257.489us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.950s	38.865us	1	1	100.00
		spi_device_csr_rw	1.970s	112.135us	1	1	100.00
		spi_device_csr_aliasing	9.970s	4.300ms	1	1	100.00
		spi_device_same_csr_outstanding	2.050s	157.885us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.950s	38.865us	1	1	100.00
		spi_device_csr_rw	1.970s	112.135us	1	1	100.00
		spi_device_csr_aliasing	9.970s	4.300ms	1	1	100.00
		spi_device_same_csr_outstanding	2.050s	157.885us	1	1	100.00
V2		TOTAL			3	22	13.64
V2S	tl_intg_err	spi_device_sec_cm			0	1	0.00
		spi_device_tl_intg_err	13.920s	3.377ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.920s	3.377ms	1	1	100.00
V2S		TOTAL			1	2	50.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds			0	1	0.00
		TOTAL			11	33	33.33

Failure Buckets

• Job killed most likely because its dependent job failed. has 22 failures:

  • Test spi_device_csb_read has 1 failures.

    • 0.spi_device_csb_read.55435203921098362141444407076624807370420280406928283658698190336150996955630
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest/run.log

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.10120496405055277496374862999286476487843418750159897910587525902476287763805
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.60359152165700364618659124553973663075201514183270860648197988698459070947034
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  • Test spi_device_tpm_read_hw_reg has 1 failures.

    • 0.spi_device_tpm_read_hw_reg.97514200217234731801316288321204828678525909445346958915758150388460415894694
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log

  • Test spi_device_tpm_all has 1 failures.

    • 0.spi_device_tpm_all.38634402491333605462641161482346553025975158752376612762302680839929483715392
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest/run.log

  • ... and 17 more tests.

• Job returned non-zero exit code has 1 failures:
  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/default/build.log

        recompiling module tb
        All of 111 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 22.909 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1