SPI_DEVICE/2P Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	25.330s	9.669ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset			0	1	0.00
V1	csr_rw	spi_device_csr_rw			0	1	0.00
V1	csr_bit_bash	spi_device_csr_bit_bash			0	1	0.00
V1	csr_aliasing	spi_device_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw			0	1	0.00
		spi_device_csr_aliasing			0	1	0.00
V1	mem_walk	spi_device_mem_walk			0	1	0.00
V1	mem_partial_access	spi_device_mem_partial_access			0	1	0.00
V1		TOTAL			1	8	12.50
V2	csb_read	spi_device_csb_read	0.720s	19.020us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	28.371s		0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.610s	45.599us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.160s	81.515us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.160s	81.515us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.200s	12.097ms	1	1	100.00
		spi_device_tpm_sts_read	0.690s	132.251us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.510s	941.694us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.170s	9.229ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.180s	17.548ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.180s	17.548ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.970s	29.658ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.970s	29.658ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.970s	29.658ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.970s	29.658ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.970s	29.658ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.700s	368.775us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.980s	1.070ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.980s	1.070ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.980s	1.070ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.110s	710.332us	1	1	100.00
		spi_device_read_buffer_direct	4.650s	3.008ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.980s	1.070ms	1	1	100.00
		spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	36.150s	10.515ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.200s	301.014us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.200s	301.014us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	25.330s	9.669ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.013m	68.721ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.840s	42.700us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.630s	14.136us	1	1	100.00
V2	intr_test	spi_device_intr_test			0	1	0.00
V2	tl_d_oob_addr_access	spi_device_tl_errors			0	1	0.00
V2	tl_d_illegal_access	spi_device_tl_errors			0	1	0.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset			0	1	0.00
		spi_device_csr_rw			0	1	0.00
		spi_device_csr_aliasing			0	1	0.00
		spi_device_same_csr_outstanding			0	1	0.00
V2	tl_d_partial_access	spi_device_csr_hw_reset			0	1	0.00
		spi_device_csr_rw			0	1	0.00
		spi_device_csr_aliasing			0	1	0.00
		spi_device_same_csr_outstanding			0	1	0.00
V2		TOTAL			18	22	81.82
V2S	tl_intg_err	spi_device_sec_cm	0.890s	263.245us	1	1	100.00
		spi_device_tl_intg_err			0	1	0.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err			0	1	0.00
V2S		TOTAL			1	2	50.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	33.730s	2.359ms	1	1	100.00
		TOTAL			21	33	63.64

Failure Buckets

• Job killed most likely because its dependent job failed. has 11 failures:

  • Test spi_device_tl_errors has 1 failures.

    • 0.spi_device_tl_errors.11398074682030112892261834934571474892908348143698161671000773634723520286839
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest/run.log

  • Test spi_device_tl_intg_err has 1 failures.

    • 0.spi_device_tl_intg_err.46530794203296194535283479543555931519052308289482401295432799757037855023131
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest/run.log

  • Test spi_device_intr_test has 1 failures.

    • 0.spi_device_intr_test.60909537499480716127376169844549859933717023214139625460394783712066863115881
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest/run.log

  • Test spi_device_mem_walk has 1 failures.

    • 0.spi_device_mem_walk.85091214076806580236178820737208183108384819970686747197593267129627826917297
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest/run.log

  • Test spi_device_mem_partial_access has 1 failures.

    • 0.spi_device_mem_partial_access.24957377285615395809148341239140523440002250263868431509038684410905920824787
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest/run.log

  • ... and 6 more tests.

• Job timed out after * minutes has 1 failures:

  • Test cover_reg_top has 1 failures.

    • cover_reg_top
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/cover_reg_top/build.log

        Job timed out after 60 minutes
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.83276196641692644911383197451661490842235658355012408896433606462426190037390
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest/run.log

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        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:05 2025
        Feature removed during lmreread, or wrong
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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255