SRAM_CTRL/MAIN Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.660s	1.390ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.610s	43.194us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.620s	14.957us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.630s	1.243ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	25.696us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.450s	2.744ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.620s	14.957us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	25.696us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.194m	10.721ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.396m	1.627ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.416m	18.611ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.005m	5.151ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.806m	276.219ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.833m	46.801ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	54.800s	13.605ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.585m	79.749ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.770s	5.885ms	1	1	100.00
		sram_ctrl_partial_access_b2b	22.506s		0	1	0.00
V2	max_throughput	sram_ctrl_max_throughput	4.760s	2.696ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.780s	7.325ms	1	1	100.00
		sram_ctrl_throughput_w_readback	3.500s	704.745us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.155m	51.437ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.880s	351.113us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.503s		0	1	0.00
V2	alert_test	sram_ctrl_alert_test	0.620s	33.325us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.680s	519.617us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.680s	519.617us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.610s	43.194us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	14.957us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	25.696us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.670s	18.388us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.610s	43.194us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	14.957us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	25.696us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.670s	18.388us	1	1	100.00
V2		TOTAL			15	17	88.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	31.850s	28.152ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
		sram_ctrl_tl_intg_err	1.820s	764.284us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.820s	764.284us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.155m	51.437ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.155m	51.437ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.620s	14.957us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.585m	79.749ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.585m	79.749ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.585m	79.749ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	54.800s	13.605ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.300s	690.126us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	31.850s	28.152ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.340s	691.709us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.660s	1.390ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.660s	1.390ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.585m	79.749ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	54.800s	13.605ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.660s	1.390ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.630s	18.952us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	32.440s	13.016ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test sram_ctrl_partial_access_b2b has 1 failures.

    • 0.sram_ctrl_partial_access_b2b.82427442671471718957349618843873154233840595315629673671198860866768517713036
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_stress_all has 1 failures.

    • 0.sram_ctrl_stress_all.50002914305466508326611659606414769335532129422480090706976532610547064225886
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.96110959183865891952626032024000179836620710542865355715695098796479885252371
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 691709441 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xa) != exp (0x46)
        UVM_INFO @ 691709441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.26030331875778952331678790042254482397750114248118717879110020541159037911413
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  18951957 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  18951957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---