SRAM_CTRL/RET Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.030s	104.860us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.610s	50.279us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.630s	12.897us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.050s	69.735us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	22.346us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.310s	157.243us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.630s	12.897us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	22.346us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.150s	343.362us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.230s	472.034us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	5.255m	34.168ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.838m	18.601ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.745s		0	1	0.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.896m	15.508ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.830s	1.535ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.762m	12.918ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	0.890s	55.094us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.534m	57.918ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	24.610s	508.555us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	36.560s	149.404us	1	1	100.00
		sram_ctrl_throughput_w_readback	11.040s	413.429us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.815m	51.498ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.660s	108.015us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	20.836m	223.168ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	17.107us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.850s	73.520us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.850s	73.520us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.610s	50.279us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	12.897us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	22.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	18.933us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.610s	50.279us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	12.897us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	22.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	18.933us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.310s	3.677ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
		sram_ctrl_tl_intg_err	26.387s		0	1	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	26.387s		0	1	0.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.815m	51.498ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.815m	51.498ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.630s	12.897us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.762m	12.918ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.762m	12.918ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.762m	12.918ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.830s	1.535ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.800s	33.753us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.310s	3.677ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.820s	127.031us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.030s	104.860us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.030s	104.860us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.762m	12.918ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.830s	1.535ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.030s	104.860us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.600s	1.757us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.552m	10.264ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 0.sram_ctrl_bijection.44979143004154172124956467727416603861569320881694479702312712584290401248747
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:02 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 0.sram_ctrl_tl_intg_err.22080603180364723407957004557675519706498681642059145319190957506030891148590
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:02 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.5606403019989956232743852153019492052368891961145594849560247322930663869977
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1756591 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1756591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.31030306299320569279407668907928700679617663777263088927712886297236344983269
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 157243262 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 157243262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---