30ac532| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 0 | 1 | 0.00 | ||
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 0 | 1 | 0.00 | ||
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 1 | 0.00 | ||
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 5.600s | 6.028ms | 1 | 1 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 3.840s | 2.059ms | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 1.785m | 39.109ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 6.180s | 2.602ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 26.177s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 3.840s | 2.059ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_aliasing | 6.180s | 2.602ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 4 | 9 | 44.44 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 1 | 0.00 | ||
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 0 | 1 | 0.00 | ||
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 1 | 0.00 | ||
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 1 | 0.00 | ||
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 0 | 1 | 0.00 | ||
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 0 | 1 | 0.00 | ||
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 1 | 0.00 | ||
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 1 | 0.00 | ||
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 1 | 0.00 | ||
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 0 | 1 | 0.00 | ||
| V2 | stress_all | sysrst_ctrl_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | sysrst_ctrl_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | sysrst_ctrl_intr_test | 1.110s | 2.052ms | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 1.950s | 2.268ms | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 1.950s | 2.268ms | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 5.600s | 6.028ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_rw | 3.840s | 2.059ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 6.180s | 2.602ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 5.390s | 5.248ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 5.600s | 6.028ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_rw | 3.840s | 2.059ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 6.180s | 2.602ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 5.390s | 5.248ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 15 | 20.00 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 0 | 1 | 0.00 | ||
| sysrst_ctrl_tl_intg_err | 20.420s | 22.335ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 20.420s | 22.335ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 8 | 27 | 29.63 |
Job killed most likely because its dependent job failed. has 18 failures:
Test sysrst_ctrl_smoke has 1 failures.
Test sysrst_ctrl_in_out_inverted has 1 failures.
Test sysrst_ctrl_combo_detect_ec_rst has 1 failures.
Test sysrst_ctrl_combo_detect_ec_rst_with_pre_cond has 1 failures.
Test sysrst_ctrl_pin_access_test has 1 failures.
... and 13 more tests.
Job returned non-zero exit code has 2 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/default/build.log
recompiling module tb
All of 82 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 17.280 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test sysrst_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
0.sysrst_ctrl_csr_mem_rw_with_rand_reset.77120219810183467490634033818828217687845272587749477093468389748213821463115
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 17:02 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255