UART Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.450s	507.947us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.760s	1.064ms	1	1	100.00
V1	csr_rw	uart_csr_rw	17.983s		0	1	0.00
V1	csr_bit_bash	uart_csr_bit_bash	1.780s	676.044us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.610s	22.942us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.890s	71.407us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	17.983s		0	1	0.00
		uart_csr_aliasing	0.610s	22.942us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	base_random_seq	uart_tx_rx	7.790s	159.513ms	1	1	100.00
V2	parity	uart_smoke	1.450s	507.947us	1	1	100.00
		uart_tx_rx	7.790s	159.513ms	1	1	100.00
V2	parity_error	uart_intr	3.550s	28.035ms	1	1	100.00
		uart_rx_parity_err	18.050s	18.764ms	1	1	100.00
V2	watermark	uart_tx_rx	7.790s	159.513ms	1	1	100.00
		uart_intr	3.550s	28.035ms	1	1	100.00
V2	fifo_full	uart_fifo_full			0	1	0.00
V2	fifo_overflow	uart_fifo_overflow	1.491m	155.939ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	10.800s	28.289ms	1	1	100.00
V2	rx_frame_err	uart_intr	3.550s	28.035ms	1	1	100.00
V2	rx_break_err	uart_intr	3.550s	28.035ms	1	1	100.00
V2	rx_timeout	uart_intr	3.550s	28.035ms	1	1	100.00
V2	perf	uart_perf	1.857m	4.116ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.450s	6.947ms	1	1	100.00
V2	line_loopback	uart_loopback	3.450s	6.947ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	6.440s	5.419ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.190s	1.685ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.820s	1.816ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.870s	4.749ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.204m	65.389ms	1	1	100.00
V2	stress_all	uart_stress_all	2.154m	537.722ms	1	1	100.00
V2	alert_test	uart_alert_test	0.560s	11.791us	1	1	100.00
V2	intr_test	uart_intr_test	0.560s	31.856us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.900s	55.763us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.900s	55.763us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.760s	1.064ms	1	1	100.00
		uart_csr_rw	17.983s		0	1	0.00
		uart_csr_aliasing	0.610s	22.942us	1	1	100.00
		uart_same_csr_outstanding	0.590s	15.804us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.760s	1.064ms	1	1	100.00
		uart_csr_rw	17.983s		0	1	0.00
		uart_csr_aliasing	0.610s	22.942us	1	1	100.00
		uart_same_csr_outstanding	0.590s	15.804us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.700s	77.336us	1	1	100.00
		uart_tl_intg_err	1.040s	97.977us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.040s	97.977us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.340s	1.935ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test uart_fifo_full has 1 failures.

    • 0.uart_fifo_full.38923368909240548912167420881947299512965751373664362247415314735454127962878
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log

        Job timed out after 60 minutes
      

• Job returned non-zero exit code has 1 failures:

  • Test uart_csr_rw has 1 failures.

    • 0.uart_csr_rw.88611282559722118287219399760593827402042324281719453622556885367044619355390
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 17 17:15 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255