CHIP Simulation Results

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	13.544s		0	1	0.00
		chip_sw_example_rom	12.829s		0	1	0.00
		chip_sw_example_manufacturer	9.427s		0	1	0.00
		chip_sw_example_concurrency	9.476s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	1	0.00
V1	csr_rw	chip_csr_rw			0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	1	0.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
		chip_csr_rw			0	1	0.00
V1	xbar_smoke	xbar_smoke	32.152s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.165m	4.747ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.165m	4.747ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.165m	4.747ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	9.446s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	9.446s		0	1	0.00
		chip_sw_uart_tx_rx_idx1	9.556s		0	1	0.00
		chip_sw_uart_tx_rx_idx2	9.608s		0	1	0.00
		chip_sw_uart_tx_rx_idx3	14.125s		0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	31.794s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.361m	7.642ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	30.618s		0	1	0.00
V1		TOTAL			2	18	11.11
V2	chip_pin_mux	chip_padctrl_attributes	27.226s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	27.226s		0	1	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	9.450s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.489s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	9.489s		0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.330m	4.435ms	1	1	100.00
		chip_tap_straps_testunlock0	2.567m	4.045ms	1	1	100.00
		chip_tap_straps_rma	31.912s		0	1	0.00
		chip_tap_straps_prod	34.398s		0	1	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	9.544s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.441s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.648s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.648s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.734m	7.152ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	13.926m	15.087ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.165m	4.332ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.927m	5.516ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.383m	18.985ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.027s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	9.159m	6.876ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.924m	2.692ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.394m	9.140ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.246ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.504m	3.486ms	1	1	100.00
		chip_sw_clkmgr_jitter	33.900s		0	1	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.213m	2.989ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	3.926m	5.924ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	2.766m	4.520ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.503m	2.976ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	2.766m	4.520ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.936m	2.755ms	1	1	100.00
		chip_sw_aes_smoketest	1.998m	3.136ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.156m	2.681ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.704m	3.116ms	1	1	100.00
		chip_sw_csrng_smoketest	2.218m	3.300ms	1	1	100.00
		chip_sw_entropy_src_smoketest	9.484m	6.742ms	1	1	100.00
		chip_sw_gpio_smoketest	2.099m	2.986ms	1	1	100.00
		chip_sw_hmac_smoketest	2.658m	2.833ms	1	1	100.00
		chip_sw_kmac_smoketest	1.962m	2.690ms	1	1	100.00
		chip_sw_otbn_smoketest	8.637m	6.651ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.056m	6.017ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.347m	6.661ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.252m	2.842ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.364m	3.646ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.569m	3.156ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.967m	3.020ms	1	1	100.00
		chip_sw_uart_smoketest	27.997s		0	1	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.085m	3.078ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.452m	4.027ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	10.835s		0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	14.701s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	40.284s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	1.937m	3.000ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.941m	3.251ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	33.138s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	32.314s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	xbar_base_random_sequence	xbar_random	11.620s	525.200us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.010s	49.153us	1	1	100.00
		xbar_smoke_large_delays	50.970s	9.197ms	1	1	100.00
		xbar_smoke_slow_rsp	43.030s	5.534ms	1	1	100.00
		xbar_random_zero_delays	4.720s	56.422us	1	1	100.00
		xbar_random_large_delays	2.696m	30.036ms	1	1	100.00
		xbar_random_slow_rsp	3.468m	26.879ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	9.650s	379.429us	1	1	100.00
		xbar_error_and_unmapped_addr	15.220s	713.849us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	10.300s	507.115us	1	1	100.00
		xbar_error_and_unmapped_addr	15.220s	713.849us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	1	0.00
		xbar_access_same_device_slow_rsp	6.966m	54.129ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	20.580s	505.455us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.684m	2.271ms	1	1	100.00
		xbar_stress_all_with_error	1.043m	1.588ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	23.423s		0	1	0.00
		xbar_stress_all_with_reset_error	27.224s		0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.701s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	55.812s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.017s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	44.985s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.956s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.755s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	36.212s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	34.775s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	33.295s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.035s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.625s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.099s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	15.336s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	14.926s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	14.313s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.572s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.724s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.982s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.172s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	10.636s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	10.035s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	9.932s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.234s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.293s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.339s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.836s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.551s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.810s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.810s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.256s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.627s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	9.804s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	9.696s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	9.850s		0	1	0.00
		rom_e2e_asm_init_dev	9.755s		0	1	0.00
		rom_e2e_asm_init_prod	9.781s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.994s		0	1	0.00
		rom_e2e_asm_init_rma	25.702s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	20.198s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	32.455m	14.714ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	17.776s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	15.736s		0	1	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	36.997s		0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	36.997s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.790m	3.726ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.027s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.606m	2.761ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.552m	2.198ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.281m	11.053ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.146m	3.126ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.373m	3.890ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	6.890m	5.258ms	1	1	100.00
		chip_plic_all_irqs_10	3.763m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20			0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.205m	3.314ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	43.928s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.030m	4.801ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.021m	2.998ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	32.567s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	26.250s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.027m	7.573ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.467m	8.443ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	42.217s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	2.727m	4.163ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.056m	6.017ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	2.727m	4.163ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	30.127s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	30.127s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	36.286s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	40.968s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.099m	6.390ms	1	1	100.00
		chip_sw_aes_idle	1.552m	2.198ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.599m	3.217ms	1	1	100.00
		chip_sw_kmac_idle	1.192m	2.216ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.382m	4.782ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.994m	4.587ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans			0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	3.029m	4.420ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	7.774m	9.673ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	38.849s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	29.150s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.045m	4.618ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.146m	4.771ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.287m	3.946ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.563m	4.320ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.734m	7.152ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.812m	6.933ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.045m	4.618ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.146m	4.771ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.165m	4.332ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.927m	5.516ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.383m	18.985ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.027s		0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	9.159m	6.876ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.924m	2.692ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.394m	9.140ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.246ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.504m	3.486ms	1	1	100.00
		chip_sw_clkmgr_jitter	33.900s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.233m	2.046ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.761m	4.785ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.080m	7.349ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	33.794s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.860m	3.142ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.784m	3.554ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	44.723s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.935m	3.526ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.550m	4.867ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.769m	24.949ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.778h	133.182ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.734m	7.152ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	26.578s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	2.834m	3.408ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	26.250s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.040m	7.453ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.227m	4.641ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.549m	5.324ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.451m	2.375ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	38.120m	18.334ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.686m	2.706ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.214m	6.579ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.686m	2.706ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.040m	7.453ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.245m	3.451ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	3.634m		0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.706m	5.295ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.927m	5.516ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	3.927m		0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en	4.165m	4.332ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	48.852m	44.892ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	3.634m		0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.425m	3.003ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	48.852m	44.892ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	6.603m	4.909ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.001m	5.914ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.001m	5.914ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.048m	3.069ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.924m	2.692ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.599m	3.217ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.161m	2.750ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	42.455s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	28.733s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	24.344s		0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	23.706s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	24.815s		0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.394m	9.140ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac			0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.281m	11.053ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	35.460m	16.786ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.031m	3.095ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.241m	2.513ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.246ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.207m	3.117ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.116m	10.353ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.192m	2.216ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.373m	3.890ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.330m	4.435ms	1	1	100.00
		chip_tap_straps_rma	31.912s		0	1	0.00
		chip_tap_straps_prod	34.398s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.088m	2.709ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	33.266s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.583m	5.491ms	1	1	100.00
		chip_sw_flash_rma_unlocked	48.852m	44.892ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.859m	3.312ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.618m	6.011ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	2.759m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	7.024m	5.921ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	36.099s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	37.676s		0	1	0.00
		chip_prim_tl_access			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.812m	6.933ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	38.849s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	29.150s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.045m	4.618ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.146m	4.771ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.287m	3.946ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.563m	4.320ms	1	1	100.00
		chip_tap_straps_dev	2.330m	4.435ms	1	1	100.00
		chip_tap_straps_rma	31.912s		0	1	0.00
		chip_tap_straps_prod	34.398s		0	1	0.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.720m	3.142ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	28.971s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.263m	3.429ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.090m	3.826ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.447m	24.184ms	1	1	100.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	49.784m	48.784ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	51.462m	48.703ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.245m	9.477ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	46.706m	45.947ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	17.447m	24.184ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	51.789s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	47.980s	2.044ms	1	1	100.00
		rom_volatile_raw_unlock	13.491s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	40.252m	16.449ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	43.383m	18.985ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.099m	6.390ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.099m	6.390ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.099m	6.390ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.357m	4.106ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	3.634m		0	1	0.00
		chip_sw_otbn_mem_scramble	3.357m	4.106ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.676m	4.181ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	33.235s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	3.634m		0	1	0.00
		chip_sw_otbn_mem_scramble	3.357m	4.106ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.235m	10.918ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.676m	4.181ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	33.235s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.604m	4.475ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.088m	2.709ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.859m	3.312ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.618m	6.011ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	2.759m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	7.024m	5.921ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.043m	5.344ms	1	1	100.00
		chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	14.211m	8.948ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	2.681m	6.993ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.062m	25.939ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	37.748s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.734m	7.089ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.053m	6.460ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.953m	24.017ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.754m	13.925ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	30.127s		0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	7.782m	10.712ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.319m	4.160ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	2.681m	6.993ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.076m	4.338ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.761m	39.363ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.801m	7.254ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.828m	6.662ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.431m	24.093ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.943m	8.383ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.690m	12.896ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.689m	29.097ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	34.096s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	36.099s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	36.099s		0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.690m	12.896ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.431m	24.093ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.319m	4.160ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.056m	6.017ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.106m	4.476ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	32.318s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.219m	5.009ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	43.928s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.023m	3.337ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.027m	7.573ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.058m	4.874ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.033m	5.416ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	1.928m	2.540ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	33.235s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	32.318s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	32.318s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	16.992m	20.521ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.407s		0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.106m	4.476ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	2.738m	3.804ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.019m	5.961ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	31.912s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	6.890m	5.258ms	1	1	100.00
		chip_plic_all_irqs_10	3.763m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20			0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.199m	2.821ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.426m	2.774ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	14.701s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	4.064m	5.344ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.712m	3.810ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	21.381s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.147s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.676m	4.181ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	3.504m	3.486ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.612m	8.275ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.034m	6.761ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	37.676s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.026s		0	1	0.00
		chip_sw_data_integrity_escalation	12.648s		0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.943m	8.383ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.074m	23.711ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.477m	3.139ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	29.634s		0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.299m	4.600ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.074m	23.711ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.074m	23.711ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.462m	11.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.462m	11.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.239m	6.060ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	36.997s		0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	10.364s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	9.814s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.549s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.550s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	9.700s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	9.697s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	10.321s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	9.647s		0	1	0.00
V2		TOTAL			156	275	56.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.461m	2.889ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.289m	2.200ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.837s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	51.984s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	29.642s		0	1	0.00
		rom_e2e_jtag_debug_dev	1.722m		0	1	0.00
		rom_e2e_jtag_debug_rma	1.946m		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	34.249s		0	1	0.00
		rom_e2e_jtag_inject_dev	1.625m		0	1	0.00
		rom_e2e_jtag_inject_rma	1.310m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.706s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.208m	5.050ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	3.636m	2.776ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.339m	5.359ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.648m	9.748ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.569m	2.387ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	40.179s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.602m	3.229ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.056m	5.436ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.028m	6.212ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	31.857s		0	1	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.690m	12.896ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	29.642s		0	1	0.00
		rom_e2e_jtag_debug_dev	1.722m		0	1	0.00
		rom_e2e_jtag_debug_rma	1.946m		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	3.956m	4.514ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.026s		0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.197h	38.331ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.197h	38.331ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	46.895s		0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	9.446s		0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	9.698s		0	1	0.00
V3		TOTAL			10	23	43.48
	Unmapped tests	chip_sival_flash_info_access	9.541s		0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	9.581s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.365m	3.256ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling			0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel	3.066m	3.641ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.836s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.496m	3.388ms	1	1	100.00
		TOTAL			173	325	53.23

Failure Buckets

• Job returned non-zero exit code has 130 failures:

  • Test chip_sw_example_flash has 1 failures.

    • 0.chip_sw_example_flash.85981291780058544998876511072202058813236261277268909369708009160060160801880
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp12329861891009096981/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp12329861891009096981/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.56778053338021070903440312147343531325232100611751998340683171406784356514700
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17261734778025305946/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17261734778025305946/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.115190689342181957507219535895773260665168268505799941646747520788796517482776
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp5329901488319754873/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp5329901488319754873/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_concurrency has 1 failures.

    • 0.chip_sw_example_concurrency.5202096434128264830636480559386859512956608566530870744753410361432303512014
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp9105323151671231697/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp9105323151671231697/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sival_flash_info_access has 1 failures.

    • 0.chip_sival_flash_info_access.50965069315734543368022711192265801238784581273073181750777427059372666856019
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17609784975306656795/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp17609784975306656795/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • ... and 125 more tests.

• Job killed most likely because its dependent job failed. has 9 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.77265886601288236461359496086574637621283169625599943651544166817729847198620
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.71648088391914030975478150651655562940925308568208782993721986176963674149273
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.108626233223501658750684513147628491075437210299260654917943168339978334576787
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.53837895123202731231688350552528535514064523790141406084652190338289450903529
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  • Test chip_prim_tl_access has 1 failures.

    • 0.chip_prim_tl_access.104322945654846196851902869612002976881899187694595071769594793696312000689439
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log

  • ... and 4 more tests.

• Job timed out after * minutes has 6 failures:

  • Test cover_reg_top has 1 failures.

    • cover_reg_top
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cover_reg_top/build.log

        Job timed out after 60 minutes
      

  • Test chip_sw_otp_ctrl_descrambling has 1 failures.

    • 0.chip_sw_otp_ctrl_descrambling.99299114049518980678779940159829310307034026252881624196621371188602686244781
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_descrambling/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_keymgr_sideload_kmac has 1 failures.

    • 0.chip_sw_keymgr_sideload_kmac.6888950588220287232278847131302150034433505556670853774574533810936104176680
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_plic_all_irqs_20 has 1 failures.

    • 0.chip_plic_all_irqs_20.87407095991991632724096233900793391953508786491415038465038837420411057670157
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.56456083366881247839427594906928012980460297760953839300941188715182863462348
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        Job timed out after 60 minutes
      

  • ... and 1 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.17650279321281683940815854991021007132715539938860174188498156100757130872777
      Line 451, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3809.736970 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3809.736970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:

  • Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.

    • 0.chip_sw_sysrst_ctrl_ec_rst_l.110055586570439047078420544754820675099579248321091475374085016215441440923559
      Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log

        UVM_ERROR @ 11983.442226 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
        UVM_INFO @ 11983.442226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 0.chip_sw_alert_test.80563136414178017534811922739182981427636236284157215858721760065553401832798
      Line 384, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 3126.186938 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
        UVM_INFO @ 3126.186938 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.8857448460640962478294092462060059402013432455086613341097097446193335623449
      Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 2997.669996 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 2997.669996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:

  • Test chip_sw_hmac_oneshot has 1 failures.

    • 0.chip_sw_hmac_oneshot.18947198863663421109217026858814482737046350131901992287693503351366252273142
      Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log

        UVM_ERROR @ 2749.667284 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
        UVM_INFO @ 2749.667284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 0.chip_sw_power_idle_load.50798178642211119660349014312177201370864990304854291030558039654495596744960
      Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 3000.058000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3000.058000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_sleep_load has 1 failures.

    • 0.chip_sw_power_sleep_load.79491837576579334556537852063824192572674742384475309137977758888568741826812
      Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

        UVM_ERROR @ 3251.323000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3251.323000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:

  • Test chip_sw_ast_clk_rst_inputs has 1 failures.

    • 0.chip_sw_ast_clk_rst_inputs.64369930335094138824839344204352304893067155936184259561302050893992162038192
      Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        UVM_ERROR @ 15087.111615 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
        UVM_INFO @ 15087.111615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---