bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 9.450s | 5.966ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 1.390s | 1.413ms | 1 | 1 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 0.860s | 647.635us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 32.360s | 27.453ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 1.670s | 1.287ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 17.907s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0.860s | 647.635us | 1 | 1 | 100.00 |
| adc_ctrl_csr_aliasing | 1.670s | 1.287ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 55.000s | 174.246ms | 1 | 1 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 8.300m | 322.598ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 3.775m | 161.183ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 12.600m | 490.601ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 3.526m | 564.994ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 36.180s | 198.276ms | 1 | 1 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 6.973m | 337.690ms | 1 | 1 | 100.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 13.018m | 500.828ms | 1 | 1 | 100.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 8.260s | 5.145ms | 1 | 1 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 36.450s | 44.608ms | 1 | 1 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 17.983s | 0 | 1 | 0.00 | |
| V2 | stress_all | adc_ctrl_stress_all | 13.559s | 0 | 1 | 0.00 | |
| V2 | alert_test | adc_ctrl_alert_test | 0.620s | 513.830us | 1 | 1 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 0.700s | 373.864us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 1.110s | 514.196us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 1.110s | 514.196us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 1.390s | 1.413ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 0.860s | 647.635us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 1.670s | 1.287ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 8.010s | 4.919ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 1.390s | 1.413ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 0.860s | 647.635us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 1.670s | 1.287ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 8.010s | 4.919ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 14 | 16 | 87.50 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 7.450s | 4.067ms | 1 | 1 | 100.00 |
| adc_ctrl_tl_intg_err | 7.560s | 4.516ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 7.560s | 4.516ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 6.060s | 3.420ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 22 | 25 | 88.00 |
Job returned non-zero exit code has 3 failures:
Test adc_ctrl_fsm_reset has 1 failures.
0.adc_ctrl_fsm_reset.111540002657422425857629991735238419366801980787922066064100107520114456819126
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:32 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_stress_all has 1 failures.
0.adc_ctrl_stress_all.55535485934873610049283580967112079299103496513122372767562580991692801304400
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:32 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
0.adc_ctrl_csr_mem_rw_with_rand_reset.98649184397700698391725242129805346341703081810608945466348419221959914722616
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:30 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255