bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 34.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 30.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 26.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 38.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 29.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |
| aes_csr_aliasing | 38.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 0 | 7 | 0.00 | |||
| V2 | algorithm | aes_smoke | 30.000s | 0 | 1 | 0.00 | |
| aes_config_error | 38.000s | 0 | 1 | 0.00 | |||
| aes_stress | 29.000s | 0 | 1 | 0.00 | |||
| V2 | key_length | aes_smoke | 30.000s | 0 | 1 | 0.00 | |
| aes_config_error | 38.000s | 0 | 1 | 0.00 | |||
| aes_stress | 29.000s | 0 | 1 | 0.00 | |||
| V2 | back2back | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| aes_b2b | 25.000s | 0 | 1 | 0.00 | |||
| V2 | backpressure | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| V2 | multi_message | aes_smoke | 30.000s | 0 | 1 | 0.00 | |
| aes_config_error | 38.000s | 0 | 1 | 0.00 | |||
| aes_stress | 29.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |||
| V2 | failure_test | aes_man_cfg_err | 33.000s | 0 | 1 | 0.00 | |
| aes_config_error | 38.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |||
| V2 | trigger_clear_test | aes_clear | 29.000s | 0 | 1 | 0.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 22.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |
| V2 | stress | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| V2 | sideload | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| aes_sideload | 21.000s | 0 | 1 | 0.00 | |||
| V2 | deinitialization | aes_deinit | 21.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | aes_stress_all | 43.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | aes_alert_test | 29.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 27.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 27.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 1 | 0.00 | |||
| aes_same_csr_outstanding | 21.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 21.000s | 0 | 1 | 0.00 | |
| aes_csr_rw | 21.000s | 0 | 1 | 0.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 1 | 0.00 | |||
| aes_same_csr_outstanding | 21.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 0 | 13 | 0.00 | |||
| V2S | reseeding | aes_reseed | 25.000s | 0 | 1 | 0.00 | |
| V2S | fault_inject | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 33.000s | 0 | 1 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 29.000s | 0 | 1 | 0.00 | |
| aes_tl_intg_err | 26.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 26.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 30.000s | 0 | 1 | 0.00 | |
| aes_stress | 29.000s | 0 | 1 | 0.00 | |||
| aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |||
| aes_core_fi | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 34.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| aes_stress | 29.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| aes_sideload | 21.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 37.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_masking | aes_stress | 29.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 21.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_ctr_fi | 17.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 26.000s | 0 | 1 | 0.00 | |
| aes_control_fi | 17.000s | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 30.000s | 0 | 1 | 0.00 | |||
| V2S | TOTAL | 0 | 11 | 0.00 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 31.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 32 | 0.00 |
Job returned non-zero exit code has 32 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.13459226654891830833560632093132612070903066196650335610051716913262797557335
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:30:10 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.104917940825124398617608008822669459426140053627073637685254225834690627859461
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:59 UTC (total: 00:00:22)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 1 failures.
0.aes_deinit.102650021543985786625210487748841267820619093732810914454185424452835192846037
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:59 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_man_cfg_err has 1 failures.
0.aes_man_cfg_err.64113921777400956197644273419743101835825141084757291957452233149227719372273
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:30:12 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_readability has 1 failures.
0.aes_readability.95117542004841225057869276856977074803989913416460702503241371713489069960219
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:30:16 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 27 more tests.