bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 38.000s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 2.000s | 57.441us | 1 | 1 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 38.000s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 26.000s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 38.000s | 0 | 1 | 0.00 | |
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | interrupts | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| V2 | alerts | csrng_alert | 20.000s | 0 | 1 | 0.00 | |
| V2 | err | csrng_err | 20.000s | 0 | 1 | 0.00 | |
| V2 | cmds | csrng_cmds | 38.000s | 0 | 1 | 0.00 | |
| V2 | life cycle | csrng_cmds | 38.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | csrng_stress_all | 25.000s | 0 | 1 | 0.00 | |
| V2 | intr_test | csrng_intr_test | 37.000s | 0 | 1 | 0.00 | |
| V2 | alert_test | csrng_alert_test | 20.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 20.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 20.000s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 2.000s | 57.441us | 1 | 1 | 100.00 |
| csrng_csr_rw | 38.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 2.000s | 57.441us | 1 | 1 | 100.00 |
| csrng_csr_rw | 38.000s | 0 | 1 | 0.00 | |||
| csrng_csr_aliasing | 21.000s | 0 | 1 | 0.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 0 | 9 | 0.00 | |||
| V2S | tl_intg_err | csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |
| csrng_tl_intg_err | 42.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 30.000s | 0 | 1 | 0.00 | |
| csrng_csr_rw | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 20.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 25.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 20.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 25.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 20.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 42.000s | 0 | 1 | 0.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| csrng_sec_cm | 38.000s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 29.000s | 0 | 1 | 0.00 | |
| csrng_err | 20.000s | 0 | 1 | 0.00 | |||
| V2S | TOTAL | 0 | 3 | 0.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 21.000s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 1 | 19 | 5.26 |
Job returned non-zero exit code has 18 failures:
Test csrng_smoke has 1 failures.
0.csrng_smoke.4932241731600031773406252619450639421867952869989157560933631338673343219872
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:27 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_cmds has 1 failures.
0.csrng_cmds.115231990229906677771946115199902324086975191339203248379940807802438365216761
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:29 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_stress_all has 1 failures.
0.csrng_stress_all.19295048466488044311759461908115216660107162406937050814397658639860158841541
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:16 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_intr has 1 failures.
0.csrng_intr.23261661496679732752806729506518024559492721366878481712465157761742371041397
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:23 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test csrng_alert has 1 failures.
0.csrng_alert.24027072093568954755602863148984363417437425033312951304976558457520260047754
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 18, 2025 at 18:29:16 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 13 more tests.