EDN Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0 1 0.00
V1 csr_hw_reset edn_csr_hw_reset 0.760s 29.557us 1 1 100.00
V1 csr_rw edn_csr_rw 17.714s 0 1 0.00
V1 csr_bit_bash edn_csr_bit_bash 2.190s 207.587us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.980s 18.489us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.350s 211.160us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 17.714s 0 1 0.00
edn_csr_aliasing 0.980s 18.489us 1 1 100.00
V1 TOTAL 4 6 66.67
V2 firmware edn_genbits 0 1 0.00
V2 csrng_commands edn_genbits 0 1 0.00
V2 genbits edn_genbits 0 1 0.00
V2 interrupts edn_intr 0 1 0.00
V2 alerts edn_alert 0 1 0.00
V2 errs edn_err 0 1 0.00
V2 disable edn_disable 0 1 0.00
edn_disable_auto_req_mode 0 1 0.00
V2 stress_all edn_stress_all 0 1 0.00
V2 intr_test edn_intr_test 22.414s 0 1 0.00
V2 alert_test edn_alert_test 0 1 0.00
V2 tl_d_oob_addr_access edn_tl_errors 1.600s 52.964us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.600s 52.964us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.760s 29.557us 1 1 100.00
edn_csr_rw 17.714s 0 1 0.00
edn_csr_aliasing 0.980s 18.489us 1 1 100.00
edn_same_csr_outstanding 0.850s 29.057us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.760s 29.557us 1 1 100.00
edn_csr_rw 17.714s 0 1 0.00
edn_csr_aliasing 0.980s 18.489us 1 1 100.00
edn_same_csr_outstanding 0.850s 29.057us 1 1 100.00
V2 TOTAL 2 11 18.18
V2S tl_intg_err edn_sec_cm 0 1 0.00
edn_tl_intg_err 1.430s 78.092us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0 1 0.00
V2S sec_cm_config_mubi edn_alert 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 0 1 0.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 0 1 0.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 0 1 0.00
V2S sec_cm_ctr_redun edn_sec_cm 0 1 0.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0 1 0.00
edn_sec_cm 0 1 0.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0 1 0.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.430s 78.092us 1 1 100.00
V2S TOTAL 1 3 33.33
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 7 21 33.33

Failure Buckets