HMAC Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.964s		0	1	0.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.790s	149.605us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.630s	58.082us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.380s	327.957us	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.110s	275.855us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	28.664s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.630s	58.082us	1	1	100.00
		hmac_csr_aliasing	2.110s	275.855us	1	1	100.00
V1		TOTAL			4	6	66.67
V2	long_msg	hmac_long_msg	45.000s	4.402ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	47.430s	2.255ms	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	7.320s	166.983us	1	1	100.00
		hmac_test_sha384_vectors	18.660s	989.521us	1	1	100.00
		hmac_test_sha512_vectors	17.430s	867.362us	1	1	100.00
		hmac_test_hmac256_vectors	8.800s	1.941ms	1	1	100.00
		hmac_test_hmac384_vectors	7.450s	1.202ms	1	1	100.00
		hmac_test_hmac512_vectors	7.410s	938.028us	1	1	100.00
V2	burst_wr	hmac_burst_wr	9.820s	3.536ms	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	2.221m	1.472ms	1	1	100.00
V2	error	hmac_error	50.070s	2.879ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	56.140s	4.895ms	1	1	100.00
V2	save_and_restore	hmac_smoke	17.964s		0	1	0.00
		hmac_long_msg	45.000s	4.402ms	1	1	100.00
		hmac_back_pressure	47.430s	2.255ms	1	1	100.00
		hmac_datapath_stress	2.221m	1.472ms	1	1	100.00
		hmac_burst_wr	9.820s	3.536ms	1	1	100.00
		hmac_stress_all	2.622m	52.101ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.964s		0	1	0.00
		hmac_long_msg	45.000s	4.402ms	1	1	100.00
		hmac_back_pressure	47.430s	2.255ms	1	1	100.00
		hmac_datapath_stress	2.221m	1.472ms	1	1	100.00
		hmac_wipe_secret	56.140s	4.895ms	1	1	100.00
		hmac_test_sha256_vectors	7.320s	166.983us	1	1	100.00
		hmac_test_sha384_vectors	18.660s	989.521us	1	1	100.00
		hmac_test_sha512_vectors	17.430s	867.362us	1	1	100.00
		hmac_test_hmac256_vectors	8.800s	1.941ms	1	1	100.00
		hmac_test_hmac384_vectors	7.450s	1.202ms	1	1	100.00
		hmac_test_hmac512_vectors	7.410s	938.028us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.964s		0	1	0.00
		hmac_long_msg	45.000s	4.402ms	1	1	100.00
		hmac_back_pressure	47.430s	2.255ms	1	1	100.00
		hmac_datapath_stress	2.221m	1.472ms	1	1	100.00
		hmac_burst_wr	9.820s	3.536ms	1	1	100.00
		hmac_error	50.070s	2.879ms	1	1	100.00
		hmac_wipe_secret	56.140s	4.895ms	1	1	100.00
		hmac_test_sha256_vectors	7.320s	166.983us	1	1	100.00
		hmac_test_sha384_vectors	18.660s	989.521us	1	1	100.00
		hmac_test_sha512_vectors	17.430s	867.362us	1	1	100.00
		hmac_test_hmac256_vectors	8.800s	1.941ms	1	1	100.00
		hmac_test_hmac384_vectors	7.450s	1.202ms	1	1	100.00
		hmac_test_hmac512_vectors	7.410s	938.028us	1	1	100.00
		hmac_stress_all	2.622m	52.101ms	1	1	100.00
V2	stress_all	hmac_stress_all	2.622m	52.101ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.510s	110.396us	1	1	100.00
V2	intr_test	hmac_intr_test	0.570s	25.851us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.410s	148.581us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.410s	148.581us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.790s	149.605us	1	1	100.00
		hmac_csr_rw	0.630s	58.082us	1	1	100.00
		hmac_csr_aliasing	2.110s	275.855us	1	1	100.00
		hmac_same_csr_outstanding	1.270s	36.785us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.790s	149.605us	1	1	100.00
		hmac_csr_rw	0.630s	58.082us	1	1	100.00
		hmac_csr_aliasing	2.110s	275.855us	1	1	100.00
		hmac_same_csr_outstanding	1.270s	36.785us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	0.930s	103.927us	1	1	100.00
		hmac_tl_intg_err	2.840s	152.054us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.840s	152.054us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.964s		0	1	0.00
V3	stress_reset	hmac_stress_reset	1.260s	242.278us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	4.388m	6.448ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.330s	22.903us	1	1	100.00
		TOTAL			26	28	92.86

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test hmac_smoke has 1 failures.

    • 0.hmac_smoke.64230371915476968953134932191392647680972213475982549864680020288975767461759
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:23 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test hmac_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.hmac_csr_mem_rw_with_rand_reset.72372427181352764922008723032250356155932625543790182668464619920437515353496
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:24 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255