bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 48.880s | 6.122ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 26.250s | 6.633ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.640s | 70.651us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.700s | 74.614us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.290s | 715.282us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.010s | 54.267us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.140s | 181.019us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.700s | 74.614us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.010s | 54.267us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.790s | 70.601us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 21.983s | 0 | 1 | 0.00 | |
| V2 | host_maxperf | i2c_host_perf | 4.764m | 12.932ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.620s | 19.595us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 45.570s | 3.361ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 32.444s | 0 | 1 | 0.00 | |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.990s | 176.911us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 3.810s | 264.584us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 34.646s | 0 | 1 | 0.00 | |||
| V2 | host_fifo_full | i2c_host_fifo_full | 1.526m | 4.368ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 7.080s | 2.927ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.470s | 399.668us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 1.830s | 499.100us | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 13.256m | 44.750ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 2.870s | 681.972us | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 19.170s | 1.587ms | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 4.390s | 2.988ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.790s | 569.847us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 0.870s | 269.176us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 4.650s | 12.386ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 19.170s | 1.587ms | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 18.723s | 0 | 1 | 0.00 | |||
| V2 | target_timeout | i2c_target_timeout | 4.160s | 5.333ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.290s | 10.054ms | 0 | 1 | 0.00 |
| V2 | bad_address | i2c_target_bad_addr | 3.100s | 2.985ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.400s | 5.918ms | 1 | 1 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.480s | 1.556ms | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.800s | 415.673us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 4.764m | 12.932ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 2.380s | 144.039us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 7.080s | 2.927ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 1.460s | 86.799us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.890s | 1.863ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.760s | 1.870ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.010s | 242.946us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 8.770s | 1.410ms | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 19.663s | 0 | 1 | 0.00 | |
| V2 | alert_test | i2c_alert_test | 0.590s | 16.015us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 22.256s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.200s | 150.260us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.200s | 150.260us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.640s | 70.651us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.700s | 74.614us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.010s | 54.267us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.760s | 40.055us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.640s | 70.651us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.700s | 74.614us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.010s | 54.267us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.760s | 40.055us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 28 | 38 | 73.68 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.110s | 85.306us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.850s | 127.944us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.110s | 85.306us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 5.130s | 428.669us | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 0.820s | 87.635us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.210s | 2.726ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 37 | 50 | 74.00 |
Job returned non-zero exit code has 6 failures:
Test i2c_host_fifo_overflow has 1 failures.
0.i2c_host_fifo_overflow.84244288598770795481126384953496681838513557062257794560959555563328164816185
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_fifo_reset_rx has 1 failures.
0.i2c_host_fifo_reset_rx.40923220595633751649175279945132995075553514166556377706683928549090133119499
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_host_stress_all has 1 failures.
0.i2c_host_stress_all.78904839597423833274521147307929473225944896027155437871961831786410170087230
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_intr_stress_wr has 1 failures.
0.i2c_target_intr_stress_wr.51234501114153356320390460607903543790086085851464555722670020692117170178263
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_smbus_maxlen has 1 failures.
0.i2c_target_smbus_maxlen.3586644151967400059386403425704027774835139030385159254882103016119363418633
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 18:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more tests.
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.101438199561763470563047835158624020573548597811325003296320833319504275079334
Line 92, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 428668764 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 428668764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.88134322161368981543094832620523743608711994454510756911555256145018550489074
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2725585821 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2725585821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:
0.i2c_host_error_intr.15784605597792468719373165132313925390449698629486266168463109960667228522359
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 70601004 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 70601004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.102326965010018231433108891429750201270346786977846971992172619023918324581445
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 499099765 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 499099765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
0.i2c_target_stretch.103962843354087250153461229477549350263082700196511212004025710429723464053427
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10054105892 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10054105892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.67462858148686039267183171068192093935869947151212463164836991574404879136182
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 87635270 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 54 [0x36])
UVM_INFO @ 87635270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:
0.i2c_host_mode_toggle.41716181182554176857944560484883102690226029179645088495587656630866065440222
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 399668083 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @89124