KEYMGR Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.540s	34.401us	1	1	100.00
V1	random	keymgr_random	37.290s	5.762ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	20.216s		0	1	0.00
V1	csr_rw	keymgr_csr_rw	20.316s		0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	3.960s	135.279us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.210s	496.605us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.650s	56.539us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	20.316s		0	1	0.00
		keymgr_csr_aliasing	7.210s	496.605us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.310s	134.749us	1	1	100.00
V2	sideload	keymgr_sideload	1.750s	194.089us	1	1	100.00
		keymgr_sideload_kmac	1.980s	60.191us	1	1	100.00
		keymgr_sideload_aes	45.050s	7.227ms	1	1	100.00
		keymgr_sideload_otbn	6.160s	836.292us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.670s	319.970us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.640s	347.906us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.370s	1.385ms	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.530s	62.609us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.900s	1.910ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.480s	68.059us	1	1	100.00
V2	stress_all	keymgr_stress_all	32.750s	2.096ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.750s	67.638us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.770s	35.133us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.430s	35.059us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.430s	35.059us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	20.216s		0	1	0.00
		keymgr_csr_rw	20.316s		0	1	0.00
		keymgr_csr_aliasing	7.210s	496.605us	1	1	100.00
		keymgr_same_csr_outstanding	2.760s	116.685us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	20.216s		0	1	0.00
		keymgr_csr_rw	20.316s		0	1	0.00
		keymgr_csr_aliasing	7.210s	496.605us	1	1	100.00
		keymgr_same_csr_outstanding	2.760s	116.685us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
		keymgr_tl_intg_err	6.810s	289.725us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.640s	285.830us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.640s	285.830us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.640s	285.830us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.640s	285.830us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.950s	422.210us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.810s	289.725us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.640s	285.830us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.310s	134.749us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.290s	5.762ms	1	1	100.00
		keymgr_csr_rw	20.316s		0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.290s	5.762ms	1	1	100.00
		keymgr_csr_rw	20.316s		0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.290s	5.762ms	1	1	100.00
		keymgr_csr_rw	20.316s		0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.640s	347.906us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.900s	1.910ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.900s	1.910ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.290s	5.762ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.570s	167.608us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.970s	127.166us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.640s	347.906us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.970s	127.166us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.970s	127.166us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.970s	127.166us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.270s	1.085ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.970s	127.166us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.320s	1.449ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test keymgr_csr_hw_reset has 1 failures.

    • 0.keymgr_csr_hw_reset.31240617734472220214638748197441548942891660350120605403727746024056693305458
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:30 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.110610775219489907360698750619034892575085377715360433432896451735951193479165
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:30 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.81872165874922027785039276396220024578797572845784173967978519987392205619887
      Line 365, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1449203600 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1449203600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---