KMAC/MASKED Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	34.420s	4.476ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.780s	49.280us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.820s	54.723us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.190s	2.397ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.570s	2.012ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.900s	324.190us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.820s	54.723us	1	1	100.00
		kmac_csr_aliasing	6.570s	2.012ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.670s	97.985us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.950s	61.699us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.622s		0	1	0.00
V2	burst_write	kmac_burst_write	2.495m	15.161ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.830s	4.209ms	1	1	100.00
		kmac_test_vectors_sha3_256	20.055m	17.510ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.030s	8.019ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.002m	153.700ms	1	1	100.00
		kmac_test_vectors_shake_128	2.403m	16.668ms	1	1	100.00
		kmac_test_vectors_shake_256	4.168m	42.464ms	1	1	100.00
		kmac_test_vectors_kmac	1.610s	156.750us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.810s	157.402us	1	1	100.00
V2	sideload	kmac_sideload	57.730s	2.893ms	1	1	100.00
V2	app	kmac_app	2.166m	33.175ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	43.090s	3.172ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	26.810s	5.120ms	1	1	100.00
V2	error	kmac_error	4.559m	36.446ms	1	1	100.00
V2	key_error	kmac_key_error	2.750s	442.331us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.790s	202.643us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.711s		0	1	0.00
V2	entropy_mode_error	kmac_entropy_mode_error	0.710s	51.927us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.080s	64.175us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.360s	73.395us	1	1	100.00
V2	stress_all	kmac_stress_all	4.587m	20.783ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.720s	19.633us	1	1	100.00
V2	alert_test	kmac_alert_test	0.730s	31.852us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.920s	115.526us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.920s	115.526us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.780s	49.280us	1	1	100.00
		kmac_csr_rw	0.820s	54.723us	1	1	100.00
		kmac_csr_aliasing	6.570s	2.012ms	1	1	100.00
		kmac_same_csr_outstanding	1.520s	169.801us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.780s	49.280us	1	1	100.00
		kmac_csr_rw	0.820s	54.723us	1	1	100.00
		kmac_csr_aliasing	6.570s	2.012ms	1	1	100.00
		kmac_same_csr_outstanding	1.520s	169.801us	1	1	100.00
V2		TOTAL			24	26	92.31
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.290s	49.053us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.290s	49.053us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.290s	49.053us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.290s	49.053us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	376.845us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	47.640s	9.366ms	1	1	100.00
		kmac_tl_intg_err	3.140s	236.334us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.140s	236.334us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.360s	73.395us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	34.420s	4.476ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	57.730s	2.893ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.290s	49.053us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	47.640s	9.366ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	47.640s	9.366ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	47.640s	9.366ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	34.420s	4.476ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.360s	73.395us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	47.640s	9.366ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	43.320s	2.826ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	34.420s	4.476ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	20.220s	1.068ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test kmac_long_msg_and_output has 1 failures.

    • 0.kmac_long_msg_and_output.46381984221628167969907002253101808369430073241125249433099708934251562237022
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:30 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test kmac_edn_timeout_error has 1 failures.

    • 0.kmac_edn_timeout_error.42215070647306862466463788106237920436212345948021249798914333033684405309008
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:30 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255