KMAC/UNMASKED Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 24.080s 2.354ms 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0.780s 56.519us 1 1 100.00
V1 csr_rw kmac_csr_rw 0.780s 21.892us 1 1 100.00
V1 csr_bit_bash kmac_csr_bit_bash 9.800s 328.871us 1 1 100.00
V1 csr_aliasing kmac_csr_aliasing 28.925s 0 1 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.150s 135.386us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0.780s 21.892us 1 1 100.00
kmac_csr_aliasing 28.925s 0 1 0.00
V1 mem_walk kmac_mem_walk 0.630s 17.250us 1 1 100.00
V1 mem_partial_access kmac_mem_partial_access 0.990s 107.376us 1 1 100.00
V1 TOTAL 7 8 87.50
V2 long_msg_and_output kmac_long_msg_and_output 10.172m 10.526ms 1 1 100.00
V2 burst_write kmac_burst_write 4.605m 4.592ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 25.759m 185.506ms 1 1 100.00
kmac_test_vectors_sha3_256 25.490s 1.646ms 1 1 100.00
kmac_test_vectors_sha3_384 18.419s 0 1 0.00
kmac_test_vectors_sha3_512 12.010s 20.749ms 1 1 100.00
kmac_test_vectors_shake_128 31.475m 446.914ms 1 1 100.00
kmac_test_vectors_shake_256 24.302m 77.592ms 1 1 100.00
kmac_test_vectors_kmac 1.420s 111.901us 1 1 100.00
kmac_test_vectors_kmac_xof 1.880s 310.029us 1 1 100.00
V2 sideload kmac_sideload 13.954s 0 1 0.00
V2 app kmac_app 2.209m 15.694ms 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 2.167m 27.310ms 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 15.604s 0 1 0.00
V2 error kmac_error 3.386m 14.949ms 1 1 100.00
V2 key_error kmac_key_error 3.230s 2.337ms 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 1.510s 41.372us 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 23.810s 1.938ms 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 11.480s 3.446ms 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 6.630s 4.082ms 1 1 100.00
V2 lc_escalation kmac_lc_escalation 1.180s 337.578us 1 1 100.00
V2 stress_all kmac_stress_all 13.854m 211.616ms 1 1 100.00
V2 intr_test kmac_intr_test 0.680s 37.756us 1 1 100.00
V2 alert_test kmac_alert_test 0.690s 20.899us 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 1.370s 248.497us 1 1 100.00
V2 tl_d_illegal_access kmac_tl_errors 1.370s 248.497us 1 1 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.780s 56.519us 1 1 100.00
kmac_csr_rw 0.780s 21.892us 1 1 100.00
kmac_csr_aliasing 28.925s 0 1 0.00
kmac_same_csr_outstanding 1.130s 108.564us 1 1 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.780s 56.519us 1 1 100.00
kmac_csr_rw 0.780s 21.892us 1 1 100.00
kmac_csr_aliasing 28.925s 0 1 0.00
kmac_same_csr_outstanding 1.130s 108.564us 1 1 100.00
V2 TOTAL 23 26 88.46
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.240s 269.609us 1 1 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.240s 269.609us 1 1 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.240s 269.609us 1 1 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.240s 269.609us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 16.294s 0 1 0.00
V2S tl_intg_err kmac_sec_cm 41.710s 21.807ms 1 1 100.00
kmac_tl_intg_err 1.760s 68.330us 1 1 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 1.760s 68.330us 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.180s 337.578us 1 1 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 24.080s 2.354ms 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 13.954s 0 1 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.240s 269.609us 1 1 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 41.710s 21.807ms 1 1 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 41.710s 21.807ms 1 1 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 41.710s 21.807ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 24.080s 2.354ms 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.180s 337.578us 1 1 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 41.710s 21.807ms 1 1 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 1.123m 11.377ms 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 24.080s 2.354ms 1 1 100.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.116m 4.756ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 35 40 87.50

Failure Buckets