ROM_CTRL/64KB Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.220s	1.397ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.300s	3.559ms	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.376s		0	1	0.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.260s	3.556ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.240s	1.076ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.810s	778.555us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.376s		0	1	0.00
		rom_ctrl_csr_aliasing	6.240s	1.076ms	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.130s	955.921us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.340s	558.986us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.660s	305.038us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	27.120s	12.452ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.960s	547.393us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	8.280s	5.818ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.240s	825.654us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.240s	825.654us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.300s	3.559ms	1	1	100.00
		rom_ctrl_csr_rw	16.376s		0	1	0.00
		rom_ctrl_csr_aliasing	6.240s	1.076ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.640s	1.107ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.300s	3.559ms	1	1	100.00
		rom_ctrl_csr_rw	16.376s		0	1	0.00
		rom_ctrl_csr_aliasing	6.240s	1.076ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.640s	1.107ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	25.150s	4.082ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
		rom_ctrl_tl_intg_err	1.515m	2.801ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.220s	1.397ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.220s	1.397ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.220s	1.397ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.515m	2.801ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
		rom_ctrl_kmac_err_chk	13.960s	547.393us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.236m	14.037ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	25.150s	4.082ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.640m	1.788ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.411m	25.045ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.5428065361370465598811028300605396972709390276977076037209446502434986263794
      Line 558, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 135831654ps failed at 135831654ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 142644210ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 142644210ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
      

• Job returned non-zero exit code has 1 failures:

  • Test rom_ctrl_csr_rw has 1 failures.

    • 0.rom_ctrl_csr_rw.53656172271017546460136017322002208042345812555730927833656159655366657777103
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255