bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.560s | 53.357us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.510s | 16.099us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.800s | 747.890us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.680s | 31.649us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.650s | 27.359us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.510s | 16.099us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.680s | 31.649us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 1 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 1 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 1 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 1 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | rv_timer_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 0.550s | 14.203us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.180s | 73.271us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.180s | 73.271us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.560s | 53.357us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.510s | 16.099us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.680s | 31.649us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.640s | 107.136us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.560s | 53.357us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.510s | 16.099us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.680s | 31.649us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.640s | 107.136us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 8 | 37.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 1 | 0.00 | ||
| rv_timer_tl_intg_err | 0.900s | 1.064ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.900s | 1.064ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | min_value | rv_timer_min | 0 | 1 | 0.00 | ||
| V3 | max_value | rv_timer_max | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 9 | 19 | 47.37 |
Job killed most likely because its dependent job failed. has 10 failures:
Test rv_timer_random has 1 failures.
Test rv_timer_min has 1 failures.
Test rv_timer_max has 1 failures.
Test rv_timer_disabled has 1 failures.
Test rv_timer_cfg_update_on_fly has 1 failures.
... and 5 more tests.
Job returned non-zero exit code has 1 failures:
default
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/default/build.log
recompiling module tb
All of 69 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 12.632 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1