SPI_DEVICE/1R1W Simulation Results

Thursday September 18 2025 18:19:06 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	18.800s	7.671ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.930s	32.680us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.190s	104.276us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.600s	7.256ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.450s	6.139ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.360s	96.784us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.190s	104.276us	1	1	100.00
		spi_device_csr_aliasing	5.450s	6.139ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	17.241us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.050s	134.897us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.680s	17.870us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.670s	8.657us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	5.625us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.370s	413.800us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.370s	413.800us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.970s		0	1	0.00
		spi_device_tpm_sts_read	0.710s	165.288us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.600s	5.367ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.570s	542.759us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.010s	157.079us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.010s	157.079us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.580s	233.029us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.580s	233.029us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.580s	233.029us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.580s	233.029us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.580s	233.029us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.410s	573.020us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.710s	278.389us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.710s	278.389us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.710s	278.389us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.550s	748.829us	1	1	100.00
		spi_device_read_buffer_direct	3.490s	2.938ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.710s	278.389us	1	1	100.00
		spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	37.530s	15.732ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.610s	417.064us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.610s	417.064us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	18.800s	7.671ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.956m	80.396ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.910s	68.678us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.630s	43.279us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.660s	13.868us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.560s	372.954us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.560s	372.954us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.930s	32.680us	1	1	100.00
		spi_device_csr_rw	1.190s	104.276us	1	1	100.00
		spi_device_csr_aliasing	5.450s	6.139ms	1	1	100.00
		spi_device_same_csr_outstanding	1.980s	406.741us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.930s	32.680us	1	1	100.00
		spi_device_csr_rw	1.190s	104.276us	1	1	100.00
		spi_device_csr_aliasing	5.450s	6.139ms	1	1	100.00
		spi_device_same_csr_outstanding	1.980s	406.741us	1	1	100.00
V2		TOTAL			19	22	86.36
V2S	tl_intg_err	spi_device_sec_cm	0.950s	103.430us	1	1	100.00
		spi_device_tl_intg_err	10.280s	2.578ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.280s	2.578ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.654m	23.087ms	0	1	0.00
		TOTAL			29	33	87.88

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.107008902009822780247298482177672029077657442935370727161137332801170643745830
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6892280 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[104])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6892280 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6892280 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.53422372235334337915925886634665031165617424705287183082601576878235416039040
      Line 83, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3142234 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x79bfa9 [11110011011111110101001] vs 0x0 [0])
        UVM_ERROR @   3176234 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb96618 [101110010110011000011000] vs 0x0 [0])
        UVM_ERROR @   3195234 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x690d2b [11010010000110100101011] vs 0x0 [0])
        UVM_ERROR @   3277234 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa2ecd1 [101000101110110011010001] vs 0x0 [0])
        UVM_ERROR @   3360234 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa7a896 [101001111010100010010110] vs 0x0 [0])
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_device_tpm_read_hw_reg has 1 failures.

    • 0.spi_device_tpm_read_hw_reg.59315828539298022487235890384894962170153206213503768792695910414562192157115
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 18:32 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 0.spi_device_flash_mode_ignore_cmds.32089770537804158185263461018287220110313143593908421020623255207447268997316
      Line 105, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 12869304259 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x9de660
        tl_ul_fuzzy_flash_status_q[i] = 0x35bfa4
        tl_ul_fuzzy_flash_status_q[i] = 0xe83d60
        tl_ul_fuzzy_flash_status_q[i] = 0x34948